Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 235 of 1136
REJ09B0109-0700
Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval
specification for the synchronous DRAM used.
When bits RTCK2 to RTCK0 are set, RTCNT starts counting up. RTCNT and RTCOR settings
should therefore be completed before setting bits RTCK2 to RTCK0. Auto refresh timing is shown
in figure 6.54.
Since the refresh counter operation is the same as the operation in the DRAM interface, see
section 6.6.12, Refresh Control.
When the continuous synchronous DRAM space is set, access to external address space other than
continuous synchronous DRAM space cannot be performed in parallel during the auto refresh
period, since the setting of the CBRM bit of REFCR is ignored.
T
Rp
SDRAMφ
RAS
CAS
WE
CKE
PALL NOPREF
A
ddress bus
T
Rr
T
Rc1
T
Rc2
Precharge-sel
High
φ
Figure 6.54 Auto Refresh Timing
When the interval specification from the PALL command to the REF command cannot be
satisfied, setting the RCW1 and RCW0 bits of REFCR enables one to three wait states to be
inserted after the T
Rp
cycle that is set by the TPC1 and TPC0 bits of DRACCR. Set the optimum
number of waits according to the synchronous DRAM connected and the operating frequency of
this LSI. Figure 6.55 shows the timing when one wait state is inserted. Since the setting of bits