Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 236 of 1136
REJ09B0109-0700
TPC1 and TPC0 of DRACCR is also valid in refresh cycles, the command interval can be
extended by the RCW1 and RCW0 bits after the precharge cycles.
T
Rp1
φ
SDRAMφ
RAS
CAS
WE
CKE
PALL NOP REF NOP
Address bus
T
Rp2
T
Rrw
T
Rr
T
Rc1
T
Rc2
Precharge-sel
High
Figure 6.55 Auto Refresh Timing
(TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1)
When the interval specification from the REF command to the ACTV cannot be satisfied, setting
the RLW1 and RLW0 bits of REFCR enables one to three wait states to be inserted in the refresh
cycle. Set the optimum number of waits according to the synchronous DRAM connected and the
operating frequency of this LSI. Figure 6.56 shows the timing when one wait state is inserted.