Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 237 of 1136
REJ09B0109-0700
T
Rp
φ
SDRAMφ
RAS
CAS
WE
CKE
PALL REF
NOP
Address bus
T
Rr
T
Rr1
T
Rcw
T
Rc2
Precharge-sel
High
Figure 6.56 Auto Refresh Timing
(TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1)
Self-Refreshing: A self-refresh mode (battery backup mode) is provided for synchronous DRAM
as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within
the synchronous DRAM.
To select self-refreshing, set the RFSHE bit to 1 in REFCR. When a SLEEP instruction is
executed to enter software standby mode, the SELF command is issued, as shown in figure 6.57.
When software standby mode is exited, the SLFRF bit in REFCR is cleared to 0 and self-refresh
mode is exited automatically. If an auto refresh request occurs when making a transition to
software standby mode, auto refreshing is executed, then self-refresh mode is entered.
When using self-refresh mode, the OPE bit must not be cleared to 0 in SBYCR.