Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 263 of 1136
REJ09B0109-0700
• Normal space access after a continuous synchronous DRAM space write access
If a normal space read cycle occurs after a continuous synchronous DRAM space write access
while the ICIS2 bit is set to 1 in BCR, idle cycle is inserted at the start of the read cycle. The
number of states of the idle cycle to be inserted is in accordance with the setting of bit IDLC.
It is not in accordance with the DRMI bit in DRACCR.
Figure 6.80 shows an example of idle cycle operation when the ICIS2 bit is set to 1.
T
p
Address bus
Idle cycle
Data bus
T
r
T
c1
T
c2
T
3
T
c1
Continuous synchronous
DRAM space write External address space read
Synchronous
DRAM space read
T
2
T
i
T
1
RAS
CAS
WE
RD
HWR, LWR
CKE
High
PALL ACTV NOP WRIT NOP
NOPREAD
DQMU, DQML
T
Cl
T
c2
Precharge-sel
φ
External address
External address
Column
address
Column address 2
Row
address
Row
address
Column
address
Figure 6.80 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2)
Table 6.11 shows whether there is an idle cycle insertion or not in the case of mixed accesses to
normal space and DRAM space/continuous synchronous DRAM space.