Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Mar. 18, 2009 page 332 of 1136
REJ09B0109-0700
7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles
Short Address Mode: Figure 7.18 shows a transfer example in which TEND output is enabled
and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external
8-bit, 2-state access space to internal I/O space.
DMA
read
A
ddress bus
φ
RD
LWR
TEND
HWR
Bus release Last transfer
cycle
DMA
write
DMA
dead
DMA
read
DMA
write
DMA
read
DMA
write
Bus release Bus release Bus
release
Figure 7.18 Example of Short Address Mode Transfer
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
In repeat mode, when TEND output is enabled, TEND output goes low in the transfer end cycle.