Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Mar. 18, 2009 page 341 of 1136
REJ09B0109-0700
DMA read
A
ddress bus
φ
DMA read DMA read
DMA
dead
RD
TEND
DACK
Bus
release
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Figure 7.27 Example of Single Address Mode (Word Read) Transfer
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.