Datasheet

Section 8 EXDMA Controller (EXDMAC)
Rev.7.00 Mar. 18, 2009 page 365 of 1136
REJ09B0109-0700
8.3.4 EXDMA Mode Control Register (EDMDR)
EDMDR controls EXDMAC operations.
Bit Bit Name Initial Value R/W Description
15 EDA 0 R/(W) EXDMA Active
Enables or disables data transfer on the
corresponding channel. When this bit is set to 1,
this indicates that an EXDMA operation is in
progress.
When auto request mode is specified (by bits
MDS1 and MDS0), transfer processing begins
when this bit is set to 1. With external requests,
transfer processing begins when a transfer request
is issued after this bit has been set to 1. When this
bit is cleared to 0 during an EXDMA operation,
transfer is halted. If this bit is cleared to 0 during an
EXDMA operation in block transfer mode, transfer
processing is continued for the currently executing
one-block transfer, and the bit is cleared on
completion of the currently executing one-block
transfer.
If an external source that ends (aborts) transfer
occurs, this bit is automatically cleared to 0 and
transfer is terminated. Do not change the operating
mode, transfer method, or other parameters while
this bit is set to 1.
0: Data transfer disabled on corresponding channel
[Clearing conditions]
• When the specified number of transfers end
• When operation is halted by a repeat area
overflow interrupt
• When 0 is written to EDA while EDA = 1
(In block transfer mode, write is effective after
end of one-block transfer)
• Reset, NMI interrupt, hardware standby mode
1: Data transfer enabled on corresponding channel
Note: The value written in the EDA bit may not be
effective immediately.