Datasheet

Section 8 EXDMA Controller (EXDMAC)
Rev.7.00 Mar. 18, 2009 page 393 of 1136
REJ09B0109-0700
8.4.9 EXDMAC Bus Cycles (Dual Address Mode)
Normal Transfer Mode (Cycle Steal Mode): Figure 8.15 shows an example of transfer when
ETEND output is enabled, and word-size, normal transfer mode (cycle steal mode) is performed
from external 16-bit, 2-state access space to external 16-bit, 2-state access space.
After one byte or word has been transferred, the bus is released. While the bus is released, one
CPU, DMAC, or DTC bus cycle is initiated.
DMA read
RD
HWR
ETEND
LWR
DMA write DMA read DMA write DMA read DMA write
A
ddress bus
φ
Bus
release
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Figure 8.15 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer