Datasheet

Section 8 EXDMA Controller (EXDMAC)
Rev.7.00 Mar. 18, 2009 page 401 of 1136
REJ09B0109-0700
After one byte or word has been transferred in response to one transfer request, the bus is released.
While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.
Single Address Mode (Write): Figure 8.24 shows an example of transfer when ETEND output is
enabled, and byte-size, single address mode transfer (write) is performed from an external device
to external 8-bit, 2-state access space.
HWR
ETEND
A
ddress bus
φ
Bus release Bus release Bus releaseLast
transfer
cycle
DMA write
EDACK
DMA writeDMA writeDMA write
Bus releaseBus release
LWR
Figure 8.24 Example of Single Address Mode (Byte Write) Transfer
Figure 8.25 shows an example of transfer when ETEND output is enabled, and word-size, single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.