Datasheet

Section 8 EXDMA Controller (EXDMAC)
Rev.7.00 Mar. 18, 2009 page 413 of 1136
REJ09B0109-0700
φ pin
EDREQ EDRAK EDACK Bus cycle ETEND
Bus release Bus release
Last transfer
in block
1-block-size transfer period
Last block
Last transfer cycle3 cycles
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
Repeated Repeated
Bus release
Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode
(No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0)