Datasheet

Section 9 Data Transfer Controller (DTC)
Rev.7.00 Mar. 18, 2009 page 426 of 1136
REJ09B0109-0700
Interrupt
request
Interrupt controller DTC
Internal address bus
DTC activation
request
Control logic
Register information
MRA MRB
CRA CRB
DAR SAR
CPU interrupt
request
On-chip
RAM
Internal data bus
Legend:
MRA, MRB
CRA, CRB
SAR
DAR
DTCERA to DTCERH
DTVECR
DTCERA
to
DTCERH
DTVECR
: DTC mode registers A and B
: DTC transfer count registers A and B
: DTC source address register
: DTC destination address register
: DTC enable registers A to H
: DTC vector register
Figure 9.1 Block Diagram of DTC