Section 9 Data Transfer Controller (DTC)
Rev.7.00 Mar. 18, 2009 page 451 of 1136
REJ09B0109-0700
First data
transfer register
information
Second data
transfer register
information
Chain transfer
(counter = 0)
Upper 8 bits
of DAR
Input buffer
Input circuit
Figure 9.13 Chain Transfer when Counter = 0
