Datasheet

Section 10 I/O Ports
Rev.7.00 Mar. 18, 2009 page 507 of 1136
REJ09B0109-0700
10.9 Port A
Port A is an 8-bit I/O port that also has other functions. The port A has the following registers.
• Port A data direction register (PADDR)
• Port A data register (PADR)
• Port A register (PORTA)
• Port A pull-up MOS control register (PAPCR)
• Port A open-drain control register (PAODR)
• Port function control register 1 (PFCR1)
10.9.1 Port A Data Direction Register (PADDR)
The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be
read; if it is, an undefined value will be read.
Bit Bit Name Initial Value R/W Description
7 PA7DDR 0 W
6 PA6DDR 0 W
5 PA5DDR 0 W
4 PA4DDR 0 W
3 PA3DDR 0 W
2 PA2DDR 0 W
1 PA1DDR 0 W
0 PA0DDR 0 W
• Modes 1 and 2
Pins PA4 to PA0 are address outputs regardless
of the PADDR settings.
For pins PA7 to PA5, when the corresponding bit
of A23E to A21E is set to 1, setting a PADDR bit
to 1 makes the corresponding port A pin an
address output, while clearing the bit to 0 makes
the pin an input port. Clearing one of bits A23E to
A
21E to 0 makes the corresponding port A pin an
I/O port, and its function can be switched with
PADDR.
• Modes 7 (when EXPE = 1) and 4
When the corresponding bit of A23E to A16E is
set to 1, setting a PADDR bit to 1 makes the
corresponding port A pin an address output,
while clearing the bit to 0 makes the pin an input
port. Clearing one of bits A23E to A16E to 0
makes the corresponding port A pin an I/O port,
and its function can be switched with PADDR.
• Mode 7 (when EXPE = 0)
Port A is an I/O port, and its pin functions can be
switched with PADDR.