Datasheet

Section 10 I/O Ports
Rev.7.00 Mar. 18, 2009 page 534 of 1136
REJ09B0109-0700
• PF1/UCAS/IRQ14/DQMU
*
2
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, and bit PF1DDR.
Operating
mode
1, 2, 4 7
EXPE ⎯ 0 1
Areas
2 to 5
Any of
areas 2
to 5 is
DRAM/
synchro-
nous
DRAM
*
2
space
Areas 2 to 5 are all
normal space
⎯ Any of
areas 2
to 5 is
DRAM/
synchro-
nous
DRAM
*
2
space
Areas 2 to 5 are all
normal space
PF1DDR ⎯ 0 1 0 1 ⎯ 0 1
Pin function UCAS/
(DQMU)
*
2
output
PF1 input PF1
output
PF1 input PF1
output
UCAS/
(DQMU)
*
2
output
PF1 input PF1
output
IRQ14 interrupt
*
1
Notes: 1. IRQ14 interrupt input when bit ITS14 in ITSR is cleared to 0.
2. Not used in the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and
H8S/2373.
• PF0/WAIT
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
WAITE in BCR, and bit PF0DDR.
Operating
mode
1, 2, 4 7
EXPE ⎯ 0 1
WAITE 0 1 ⎯ 0 1
PF0DDR 0 1 ⎯ 0 1 0 1 ⎯
Pin function PF0 input PF0
output
WAIT
input
PF0
input
PF0
output
PF0 input PF0 output WAIT input