Datasheet

Rev.7.00 Mar. 18, 2009 page lix of lxvi
REJ09B0109-0700
Tables
Section 1 Overview................................................................................................1
Table 1.1 Pin Arrangement in Each Operating Mode ............................................................... 12
Table 1.2 Pin Functions............................................................................................................. 18
Section 2 CPU......................................................................................................35
Table 2.1 Instruction Classification........................................................................................... 51
Table 2.2 Operation Notation.................................................................................................... 52
Table 2.3 Data Transfer Instructions......................................................................................... 53
Table 2.4 Arithmetic Operations Instructions ........................................................................... 54
Table 2.5 Logic Operations Instructions ................................................................................... 56
Table 2.6 Shift Instructions ....................................................................................................... 56
Table 2.7 Bit Manipulation Instructions.................................................................................... 57
Table 2.8 Branch Instructions ................................................................................................... 59
Table 2.9 System Control Instructions ...................................................................................... 60
Table 2.10 Block Data Transfer Instructions............................................................................... 61
Table 2.11 Addressing Modes..................................................................................................... 63
Table 2.12 Absolute Address Access Ranges ............................................................................. 64
Table 2.13 Effective Address Calculation................................................................................... 66
Section 3 MCU Operating Modes........................................................................71
Table 3.1 MCU Operating Mode Selection............................................................................... 71
Table 3.2 Pin Functions in Each Operating Mode..................................................................... 77
Section 4 Exception Handling .............................................................................93
Table 4.1 Exception Types and Priority.................................................................................... 93
Table 4.2 Exception Handling Vector Table............................................................................. 94
Table 4.3 Status of CCR and EXR after Trace Exception Handling......................................... 98
Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling ........................ 99
Section 5 Interrupt Controller............................................................................103
Table 5.1 Pin Configuration.................................................................................................... 105
Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities................................. 122
Table 5.3 Interrupt Control Modes.......................................................................................... 127
Table 5.4 Interrupt Response Times........................................................................................ 132
Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses...................... 133
Section 6 Bus Controller (BSC).........................................................................137
Table 6.1 Pin Configuration.................................................................................................... 139