Datasheet

Rev.7.00 Mar. 18, 2009 page lx of lxvi
REJ09B0109-0700
Table 6.2 Bus Specifications for Each Area (Basic Bus Interface)......................................... 173
Table 6.3 Data Buses Used and Valid Strobes........................................................................ 178
Table 6.4 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space.............. 191
Table 6.5 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing..... 192
Table 6.6 DRAM Interface Pins.............................................................................................. 193
Table 6.7 Relation between Settings of Bits RMTS2 to RMTS0
and Synchronous DRAM Space.............................................................................. 216
Table 6.8 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing..... 217
Table 6.9 Synchronous DRAM Interface Pins ........................................................................ 219
Table 6.10 Setting CAS Latency............................................................................................... 222
Table 6.11 Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous
Synchronous DRAM Space..................................................................................... 264
Table 6.12 Pin States in Idle Cycle ........................................................................................... 268
Table 6.13 Pin States in Bus Released State ............................................................................. 271
Section 7 DMA Controller (DMAC).................................................................279
Table 7.1 Pin Configuration.................................................................................................... 281
Table 7.2 Short Address Mode and Full Address Mode (Channel 0)...................................... 282
Table 7.3 DMAC Activation Sources ..................................................................................... 307
Table 7.4 DMAC Transfer Modes........................................................................................... 310
Table 7.5 Register Functions in Sequential Mode................................................................... 312
Table 7.6 Register Functions in Idle Mode ............................................................................. 315
Table 7.7 Register Functions in Repeat Mode ........................................................................ 317
Table 7.8 Register Functions in Single Address Mode ........................................................... 320
Table 7.9 Register Functions in Normal Mode ....................................................................... 323
Table 7.10 Register Functions in Block Transfer Mode............................................................ 326
Table 7.11 DMAC Channel Priority Order ............................................................................... 347
Table 7.12 Interrupt Sources and Priority Order ....................................................................... 353
Section 8 EXDMA Controller (EXDMAC) ...................................................... 359
Table 8.1 Pin Configuration.................................................................................................... 361
Table 8.2 EXDMAC Transfer Modes ..................................................................................... 374
Table 8.3 EXDMAC Channel Priority Order.......................................................................... 390
Table 8.4 Interrupt Sources and Priority Order ....................................................................... 420
Section 9 Data Transfer Controller (DTC)........................................................ 425
Table 9.1 Relationship between Activation Sources and DTCER Clearing............................ 432
Table 9.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs................. 435
Table 9.3 Chain Transfer Conditions ...................................................................................... 439
Table 9.4 Register Function in Normal Mode......................................................................... 440
Table 9.5 Register Function in Repeat Mode.......................................................................... 441