Datasheet

Rev.7.00 Mar. 18, 2009 page lxi of lxvi

REJ09B0109-0700

Table 9.6 Register Function in Block Transfer Mode............................................................. 442

Table 9.7 DTC Execution Status............................................................................................. 446

Table 9.8 Number of States Required for Each Execution Status........................................... 446

Section 10 I/O Ports...........................................................................................455

Table 10.1 Port Functions ......................................................................................................... 456

Table 10.2 Input Pull-Up MOS States (Port A)......................................................................... 512

Table 10.3 Input Pull-Up MOS States (Port B)......................................................................... 516

Table 10.4 Input Pull-Up MOS States (Port C)........................................................................ 520

Table 10.5 Input Pull-Up MOS States (Port D)......................................................................... 524

Table 10.6 Input Pull-Up MOS States (Port E)......................................................................... 528

Section 11 16-Bit Timer Pulse Unit (TPU)........................................................545

Table 11.1 TPU Functions......................................................................................................... 546

Table 11.2 Pin Configuration.................................................................................................... 549

Table 11.3 CCLR2 to CCLR0 (Channels 0 and 3).................................................................... 553

Table 11.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)........................................................... 553

Table 11.5 TPSC2 to TPSC0 (Channel 0)................................................................................. 554

Table 11.6 TPSC2 to TPSC0 (Channel 1)................................................................................. 554

Table 11.7 TPSC2 to TPSC0 (Channel 2)................................................................................. 555

Table 11.8 TPSC2 to TPSC0 (Channel 3)................................................................................. 555

Table 11.9 TPSC2 to TPSC0 (Channel 4)................................................................................. 556

Table 11.10 TPSC2 to TPSC0 (Channel 5)................................................................................. 556

Table 11.11 MD3 to MD0........................................................................................................... 558

Table 11.12 TIORH_0................................................................................................................. 560

Table 11.13 TIORL_0................................................................................................................. 561

Table 11.14 TIOR_1 ................................................................................................................... 562

Table 11.15 TIOR_2 ................................................................................................................... 563

Table 11.16 TIORH_3................................................................................................................. 564

Table 11.17 TIORL_3................................................................................................................. 565

Table 11.18 TIOR_4 ................................................................................................................... 566

Table 11.19 TIOR_5 ................................................................................................................... 567

Table 11.20 TIORH_0................................................................................................................. 568

Table 11.21 TIORL_0................................................................................................................. 569

Table 11.22 TIOR_1 ................................................................................................................... 570

Table 11.23 TIOR_2 ................................................................................................................... 571

Table 11.24 TIORH_3................................................................................................................. 572

Table 11.25 TIORL_3................................................................................................................. 573

Table 11.26 TIOR_4 ................................................................................................................... 574

Table 11.27 TIOR_5 ................................................................................................................... 575

Table 11.28 Register Combinations in Buffer Operation............................................................ 592