Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Mar. 18, 2009 page 621 of 1136
REJ09B0109-0700
11.10.5 Contention between TCNT Write and Increment Operations
If incrementing occurs in the T
2
state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented. Figure 11.46 shows the timing in this case.
TCNT input
clock
Write signal
A
ddress
φ
TCNT address
TCNT
TCNT write cycle
T
1
T
2
N M
TCNT write data
Figure 11.46 Contention between TCNT Write and Increment Operations