Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Mar. 18, 2009 page 623 of 1136
REJ09B0109-0700
11.10.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T
2
state of a TGR write cycle, the data transferred to TGR by the
buffer operation will be the data prior to the write.
Figure 11.48 shows the timing in this case.
Compare
match signal
Write signal
A
ddress
φ
Buffer register
address
Buffer
register
TGR write cycle
T
1
T
2
N
TGR
N M
Buffer register write data
Figure 11.48 Contention between Buffer Register Write and Compare Match