Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Mar. 18, 2009 page 628 of 1136
REJ09B0109-0700
11.10.12 Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T
2
state of a TCNT write cycle, when
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 11.53 shows the operation timing when there is contention between TCNT write and
overflow.
Write signal
A
ddress
φ
TCNT address
TCNT
TCNT write cycle
T
1
T
2
H'FFFF M
TCNT write data
TCFV flag
Figure 11.53 Contention between TCNT Write and Overflow