Datasheet

Section 16 I
2
C Bus Interface 2 (IIC2) (Option)
Rev.7.00 Mar. 18, 2009 page 778 of 1136
REJ09B0109-0700
Bit Bit Name Initial Value R/W Description
1 IICRST 0 R/W IIC control part reset
This bit resets control parts except for I
2
C registers.
If this bit is set to 1 when hang-up is occurred
because of communication failure during I
2
C
operation, I
2
C control part can be reset without
setting ports and initializing registers.
0 ⎯ 1 ⎯ Reserved
This bit is always read as 1.
16.3.3 I
2
C Bus Mode Register (ICMR)
ICMR controls the master mode wait and selects the number of transfer bits.
Bit Bit Name Initial Value R/W Description
7 MLS 0 R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
6 WAIT 0 R/W Wait Insertion Bit
This bit selects whether to insert a wait after data
transfer except for the acknowledge bit. When
WAIT is set to 1, after the fall of the clock for the
final data bit, low period is extended for two transfer
clocks. If WAIT is cleared to 0, data and
acknowledge bits are transferred consecutively with
no wait inserted.
The setting of this bit is invalid in slave mode.
5, 4
⎯ All 1
⎯ Reserved
These bits are always read as 1.
3 BCWP 1 R/W BC Write Protect
This bit controls the BC2 to BC0 modifications.
When modifying BC2 to BC0, this bit should be
cleared to 0 and use the MOV instruction.
0: When writing, values of BC2 to BC0 are set.
1: When reading, 1 is always read.
When writing, settings of BC2 to BC0 are invalid.