Datasheet

Section 16 I

C Bus Interface 2 (IIC2) (Option)

Rev.7.00 Mar. 18, 2009 page 802 of 1136

REJ09B0109-0700

16.6 Bit Synchronous Circuit

In master mode,

• When SCL is driven to low by the slave device

• When the rising speed of SCL is lower by the load of the SCL line (load capacitance or pull-up

resistance)

This module has a possibility that high level period may be short in the two states described

above. Therefore it monitors SCL and communicates by bit with synchronization.

Figure 16.18 shows the timing of the bit synchronous circuit and table 16.4 shows the time when

SCL output changes from low to Hi-Z then SCL is monitored.

SCL

VIH

SCL monitor

timing reference

clock

Internal SCL

Figure 16.18 Timing of the Bit Synchronous Circuit

Table 16.4 Time for monitoring SCL

CKS3 CKS2 Time for monitoring SCL

0 7.5 tcyc

1 19.5 tcyc

1 0 17.5 tcyc

1 41.5 tcyc