Datasheet

Section 17 A/D Converter
Rev.7.00 Mar. 18, 2009 page 814 of 1136
REJ09B0109-0700
(1)
(2)
t
D
t
SPL
t
CONV
A
ddress
φ
Write signal
Input sampling
timing
A
DF
Legend:
(1) : ADCSR write cycle
(2) : ADCSR address
t
D
: A/D conversion start delay time
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
Figure 17.2 A/D Conversion Timing
Table 17.3 A/D Conversion Time (Single Mode)
CKS1 = 0 CKS1 = 1
CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1
Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max
A/D conversion
start delay time
t
D
18 — 33 10 — 17 6 — 9 4 — 5
Input sampling
time
t
SPL
— 127 — — 63 — — 31 — — 15 —
A/D conversion
time
t
CONV
515 — 530 259 — 266 131 — 134 67 — 68
Note: Values in the table are the number of states.