Datasheet

Section 17 A/D Converter
Rev.7.00 Mar. 18, 2009 page 815 of 1136
REJ09B0109-0700
Table 17.4 A/D Conversion Time (Scan Mode)
CKS1 CKS0 Conversion Time (State)
0 512 (Fixed) 0
1 256 (Fixed)
1 0 128 (Fixed)
1 64 (Fixed)
17.4.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as when the bit ADST has been set to 1 by software. Figure 17.3 shows the
timing.
ADTRG
Internal trigger signal
φ
A
DST
A/D conversion
Figure 17.3 External Trigger Input Timing