Datasheet

Rev.7.00 Mar. 18, 2009 page vii of lxvi
REJ09B0109-0700
Main Revisions for This Edition
Item Page Revision (See Manual for Details)
3.4 Memory Map in
Each Operating Mode
Figure 3.2 Memory
Map for H8S/2378 and
H8S/2378R (2)
79 Figure amended
ROM: 512 kbytes
RAM: 32 kbytes
Mode 5
(User boot mode)
H'000000
H'080000H'080000
ROM: 512 kbytes
RAM: 32 kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
H'000000
On-chip ROM
On-chip ROM
ROM: 512 kbytes
RAM: 32 kbytes
Mode 7
(Single-chip activation
expanded mode,
with on-chip ROM enabled)
H'000000
H'080000
On-chip ROM
Figure 3.7 Memory
Map for H8S/2374 and
H8S/2374R (1)
84 Figure amended
H'FF4000
H'FFC000
On-chip RAM/
external address
space
*
1
H'FF4000
H'FFC000
On-chip RAM
*
3
Figure 3.15 Memory
Map for H8S/2370 and
H8S/2370R (2)
92 Figure amended
H'FF4000
H'FFC000
*
5
H'FF4000
H'FFC000
On-chip RAM/
external address
space
*
1
On-chip RAM
H'FF4000
H'FF8000
H'FF8000
H'FF8000
H'FFC000
Reserved area
*
4
Reserved area
*
4
Reserved area
*
4
On-chip RAM/
external address
space
*
3
6.7.11 Byte Access
Control
Figure 6.51 Example
of DQMU and DQML
Byte Control
230 Figure amended
This LSI
(Address shift size set to 8 bits)
CS2 (RAS)
CS3 (CAS)
64-Mbit synchronous DRAM
1 Mword × 16 bits × 4-bank configuration
8-bit column address
RAS
CAS
6.9.2 Pin States in
Idle Cycle
Table 6.12 Pin States
in Idle Cycle
268 Table amended
Pins Pin State
EDACKn (n = 3, 2)
High
7.3.7 DMA Terminal
Control Register
(DMATCR)
306 Description amended
… The TEND pin is available only for channel B in short
address mode.