Datasheet

Section 21 Flash Memory (0.18-μm F-ZTAT Version)
Rev.7.00 Mar. 18, 2009 page 872 of 1136
REJ09B0109-0700
Table 21.3 Register/Parameter and Target Mode
Download
Initiali-
zation
Program-
ming Erasure Read
FCCS
⎯ ⎯ ⎯ ⎯
FPCS ⎯ ⎯ ⎯ ⎯
FECS ⎯ ⎯ ⎯ ⎯
FKEY ⎯ ⎯
FMATS ⎯ ⎯
*
1
*
1
*
2
Programming/erasing
interface register
FTDAR
⎯ ⎯ ⎯ ⎯
DPFR ⎯ ⎯ ⎯ ⎯
FPFR ⎯ ⎯
FPEFEQ ⎯ ⎯ ⎯ ⎯
FUBRA ⎯ ⎯ ⎯ ⎯
FMPAR ⎯ ⎯ ⎯ ⎯
Programming/erasing
interface parameter
FMPDR ⎯ ⎯ ⎯ ⎯
FEBS ⎯ ⎯ ⎯ ⎯
Notes: 1. The setting is required when programming or erasing user MAT in user boot mode.
2. The setting may be required according to the combination of initiation mode and read
target MAT.
21.3.1 Programming/Erasing Interface Register
The programming/erasing interface registers are as described below. They are all 8-bit registers
that can be accessed in byte. Except for the FLER bit in FCCS, these registers are initialized at a
power-on reset, in hardware standby mode, or in software standby mode. The FLER bit is not
initialized in software standby mode.
• Flash Code Control and Status Register (FCCS)
FCCS is used to request monitoring of flash memory programming/erase errors or
downloading of on-chip programs.