To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual 16 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 5. Contents 6. Overview 7.
Preface The H8S/2378 Group and H8S/2378R Group microcomputers (MCU) made up of the H8S/2000 CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a 16-Mbyte linear address space.
In order to understand the details of the CPU’s functions Read the H8S/2600 Series, H8S/2000 Series Software Manual. For the execution state of each instruction in this LSI, see Appendix D, Bus State during Execution of Instructions. In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register.
Main Revisions for This Edition Item Page Revision (See Manual for Details) 3.4 Memory Map in Each Operating Mode 79 Figure amended ROM: 512 kbytes RAM: 32 kbytes Mode 5 (User boot mode) ROM: 512 kbytes RAM: 32 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) Figure 3.2 Memory Map for H8S/2378 and H8S/2378R (2) H'000000 H'000000 On-chip ROM 84 H'000000 On-chip ROM H'080000 Figure 3.
Item Page Revision (See Manual for Details) Section 8 EXDMA Controller (EXDMAC) 359 Description amended 8.3.5 EXDMA Address Control Register (EDACR) 370 … The EXDMAC can carry out high-speed data transfer, in place of the CPU, to and from external devices and external memory with a DACK (DMA transfer notification) facility.
Item Page Revision (See Manual for Details) 8.4.2 Address Modes 377 Figure amended Figure 8.3 Data Flow in Single Address Mode External memory External device with DACK Figure 8.
Item Page Revision (See Manual for Details) 9.8.5 Chain Transfer 453 Description amended … SCI and A/D converter interrupt/activation sources, on the other hand, are cleared when the DTC reads or writes to the prescribed register. 10.1.4 Pin Functions 471 • P10/PO8/TIOCA0 Table amended TPU channel 0 settings (1) in table below Pin function (2) in table below TIOCA0 output P10 input P10 output PO8 output TIOCA0 input *1 10.9.
Item Page Revision (See Manual for Details) 10.12.5 Pin Functions 523 Table amended PDnDDR Pin function — 0 1 — Data I/O PDn input PDn output Data I/O Legend added Legend: n = 7 to 0 10.13.5 Pin Functions 527 Table amended PEnDDR Pin function 0 1 — 0 1 0 1 — PEn input PEn output Data I/O PEn input PEn output PEn input PEn output Data I/O Legend added Legend: n = 7 to 0 10.14.4 Pin Functions 531 • PF7/φ 10.16.
Item Page Revision (See Manual for Details) 15.3.9 Bit Rate Register (BRR) 712 Table amended Operating Frequency φ (MHz) Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) 8 Bit Rate (bit/s) n 9.8304 Error (%) N n 10 Error (%) N n 12 Error (%) N n N Error (%) 9600 0 25 0.16 0 31 0.00 0 32 –1.36 0 38 0.16 19200 0 12 0.16 0 15 0.00 0 15 1.73 0 19 –2.34 31250 0 7 0.00 0 9 –1.70 0 9 0.00 0 11 0.00 38400 — — — 0 7 0.00 0 7 1.
Item Page Revision (See Manual for Details) 15.4.4 SCI Initialization (Asynchronous Mode) 727 Description added 15.6.2 SCI Initialization (Clocked Synchronous Mode) 741 2 Section 16 I C Bus Interface 2 (IIC2) (Option) 2 Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 15.5. Do not write to SMR, SCMR, IrCR, or SEMR while the SCI is operating.
Item Page Revision (See Manual for Details) 16.3.
Item Page Revision (See Manual for Details) 16.4.7 Example of Use 798 Figure amended [14] Clear RCVD to 0. Figure 16.15 Sample Flowchart for Master Receive Mode Read RDRF in ICSR No [9] RDRF=1 ? [15] Clear ACKBT. [16] Set slave receive mode. Yes Clear STOP of ICSR [10] Write BBSY = 0 and SCP = 0 [11] Read STOP of ICSR No [12] STOP=1 ? Yes Read ICDRR [13] Set RCVD = 0 (ICCRA) [14] Clear ACKBT in ICIER [15] Set MST = 0 (ICCRA) [16] End Figure 16.
Item Page Revision (See Manual for Details) 17.1 Features 806 Figure amended Figure 17.1 Block Diagram of A/D Converter AVCC Vref 10-bit D/A AVSS 21.1 Features 862 Description amended • Programming/erase protection There are three types of flash memory programming/erase protection that may be selected: hardware protection, software protection, and error protection. 21.1.1 Operating Mode 864 21.3.1 Programming/ Erasing Interface Register 872 21.3.
Item Page Revision (See Manual for Details) 21.4.2 User Program Mode 889 Description amended …For details on the frequency setting, see the description in 21.3.2 (2) (a), Flash programming/erasing frequency parameter (FPEFEQ: general register ER0 of CPU). (2) Programming Procedure in User Program Mode …For details, see the descriptions in 21.3.2 (2) (a), Flash programming/erasing frequency parameter (FPEFEQ: general register ER0 of CPU), and 21.3.
Item Page Revision (See Manual for Details) 26.1.2 DC Characteristics 1020 Table amended Symbol Min. Typ. Max. Test Unit Conditions VIH VCC × 0.9 — VCC +0.3 V RES, NMI, EMLE VCC × 0.9 — VCC +0.3 V EXTAL VCC × 0.7 — VCC +0.3 V Port 3, 3 P50 to P53* , 3 3 ports 6* and 8* , 3 ports A to H* 2.2 — VCC +0.3 V 2.2 — AVCC +0.3 V –0.3 — VCC × 0.1 V Item Table 26.
Item Page Revision (See Manual for Details) 26.2.2 DC Characteristics 1036 Table amended Symbol Min. Typ. Max. Test Unit Conditions VIH VCC × 0.9 — VCC +0.3 V RES, NMI, EMLE VCC × 0.9 — VCC +0.3 V EXTAL VCC × 0.7 — VCC +0.3 V Port 3, 3 P50 to P53* , 3 3 ports 6* and 8* , 3 ports A to H* 2.2 — VCC +0.3 V 2.2 — AVCC +0.3 V –0.3 — VCC × 0.1 V Item Table 26.
Item Page Revision (See Manual for Details) 26.3.2 DC Characteristics 1051 Table amended Symbol Min. Typ. Max. Test Unit Conditions VIH VCC × 0.9 — VCC +0.3 V RES, NMI, EMLE VCC × 0.9 — VCC +0.3 V EXTAL VCC × 0.7 — VCC +0.3 V Port 3, 3 P50 to P53* , 3 3 ports 6* and 8* , 3 ports A to H* 2.2 — VCC +0.3 V 2.2 — AVCC +0.3 V –0.3 — VCC × 0.1 V Item Table 26.
Item Page Revision (See Manual for Details) 26.4.3 Bus Timing 1074 Figure amended Figure 26.11 Basic Bus Timing: ThreeState Access (CS Assertion Period Extended) Figure 26.14 DRAM Access Timing: TwoState Access tEDACD2 tEDACD1 EDACK2, EDACK3 1077 Figure amended tEDACD2 tEDACD1 EDACK2, EDACK3 Figure 26.15 DRAM Access Timing: TwoState Access, One Wait 1078 Figure 26.
Item Page Revision (See Manual for Details) 26.4.4 DMAC and EXDMAC Timing 1090 Figure amended tETED Figure 26.30 DMAC and EXDMAC TEND/ETEND Output Timing Figure 26.31 DMAC and EXDMAC DREQ/EDREQ Input Timing tETED ETEND2, ETEND3 1090 Figure amended tEDRQS tDERQH EDREQ2, EDREQ3 Figure 26.32 EXDMAC EDRAK Output Timing 1090 Figure amended tEDRKD EDRAK2, EDRAK3 C. Package Dimensions 1107 Figure replaced Figure C.
Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 Features .................................................................................................................................. 1 Block Diagram ....................................................................................................................... 3 Pin Description.................................................................................
2.8 2.9 2.7.9 Effective Address Calculation ................................................................................ 66 Processing States.................................................................................................................. 68 Usage Note........................................................................................................................... 69 2.9.1 Note on Bit Manipulation Instructions....................................................................
5.4 5.5 5.6 5.7 5.3.5 IRQ Status Register (ISR)..................................................................................... 116 5.3.6 IRQ Pin Select Register (ITSR) ............................................................................ 117 5.3.7 Software Standby Release IRQ Enable Register (SSIER) .................................... 119 Interrupt Sources ................................................................................................................ 120 5.4.
6.5 6.6 6.7 6.4.2 Bus Specifications................................................................................................. 172 6.4.3 Memory Interfaces ................................................................................................ 174 6.4.4 Chip Select Signals ............................................................................................... 175 Basic Bus Interface ....................................................................................................
6.8 6.9 6.10 6.11 6.12 6.13 6.14 Burst ROM Interface.......................................................................................................... 246 6.8.1 Basic Timing......................................................................................................... 246 6.8.2 Wait Control ......................................................................................................... 248 6.8.3 Write Access ....................................................................
7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 7.5.10 7.5.11 7.5.12 7.5.13 7.6 7.7 Idle Mode.............................................................................................................. 314 Repeat Mode ......................................................................................................... 316 Single Address Mode............................................................................................ 320 Normal Mode...........................................................
8.5 8.6 8.4.6 Repeat Area Function ........................................................................................... 383 8.4.7 Registers during DMA Transfer Operation........................................................... 385 8.4.8 Channel Priority Order.......................................................................................... 390 8.4.9 EXDMAC Bus Cycles (Dual Address Mode)....................................................... 393 8.4.
9.7 9.8 Examples of Use of the DTC ............................................................................................. 448 9.7.1 Normal Mode........................................................................................................ 448 9.7.2 Chain Transfer ...................................................................................................... 449 9.7.3 Chain Transfer when Counter = 0......................................................................... 450 9.7.
10.7 10.8 10.9 10.10 10.11 10.12 10.13 10.6.3 Port 6 Register (PORT6)....................................................................................... 495 10.6.4 Pin Functions ........................................................................................................ 496 Port 8.................................................................................................................................. 499 10.7.1 Port 8 Data Direction Register (P8DDR)............................
10.13.1 Port E Data Direction Register (PEDDR) ............................................................. 525 10.13.2 Port E Data Register (PEDR)................................................................................ 526 10.13.3 Port E Register (PORTE)...................................................................................... 526 10.13.4 Port E Pull-up Control Register (PEPCR) ............................................................ 527 10.13.5 Pin Functions ......................
11.5 11.6 11.7 11.8 11.9 11.10 11.4.5 PWM Modes ......................................................................................................... 598 11.4.6 Phase Counting Mode ........................................................................................... 603 Interrupt Sources ................................................................................................................ 609 DTC Activation................................................................................
12.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) .......................................................... 648 12.4.7 Inverted Pulse Output ........................................................................................... 650 12.4.8 Pulse Output Triggered by Input Capture ............................................................. 651 12.5 Usage Notes ......................................................................................
Section 14 Watchdog Timer (WDT)..................................................................677 14.1 Features .............................................................................................................................. 677 14.2 Input/Output Pin................................................................................................................. 678 14.3 Register Descriptions ....................................................................................................
15.4.6 Serial Data Reception (Asynchronous Mode)....................................................... 730 15.5 Multiprocessor Communication Function.......................................................................... 734 15.5.1 Multiprocessor Serial Data Transmission ............................................................. 735 15.5.2 Multiprocessor Serial Data Reception .................................................................. 737 15.6 Operation in Clocked Synchronous Mode ............
16.4 16.5 16.6 16.7 16.3.4 I2C Bus Interrupt Enable Register (ICIER)........................................................... 780 16.3.5 I2C Bus Status Register (ICSR) ............................................................................ 782 16.3.6 Slave address register (SAR) ................................................................................ 784 16.3.7 I2C Bus Transmit Data Register (ICDRT) ............................................................ 785 16.3.
Section 18 D/A Converter ................................................................................. 821 18.1 Features .............................................................................................................................. 821 18.2 Input/Output Pins ............................................................................................................... 824 18.3 Register Descriptions ..........................................................................................
21.2 21.3 21.4 21.5 21.6 21.7 21.8 21.9 21.1.1 Operating Mode .................................................................................................... 864 21.1.2 Mode Comparison................................................................................................. 865 21.1.3 Flash MAT Configuration..................................................................................... 866 21.1.4 Block Division ...........................................................................
Section 24 Power-Down Modes ........................................................................ 965 24.1 Register Descriptions ......................................................................................................... 968 24.1.1 Standby Control Register (SBYCR) ..................................................................... 968 24.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)..................... 970 24.1.
26.2.3 AC Characteristics .............................................................................................. 1039 26.2.4 A/D Conversion Characteristics.......................................................................... 1048 26.2.5 D/A Conversion Characteristics.......................................................................... 1048 26.2.6 Flash Memory Characteristics ............................................................................ 1049 26.
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Figures Section 1 Overview................................................................................................1 Figure 1.1 Figure 1.2 Figure 1.3 Figure 1.4 Figure 1.5 Figure 1.6 Figure 1.7 Figure 1.8 Figure 1.9 Internal Block Diagram for H8S/2378 0.18μm F-ZTAT Group and H8S/2378R 0.18μm F-ZTAT Group .................................................................... 3 Internal Block Diagram for H8S/2377 and H8S/2377R..............................................
Figure 3.9 Figure 3.10 Figure 3.11 Figure 3.12 Figure 3.13 Figure 3.14 Figure 3.15 Memory Map for H8S/2373 and H8S/2373R............................................................ 86 Memory Map for H8S/2372 and H8S/2372R (1) ...................................................... 87 Memory Map for H8S/2372 and H8S/2372R (2) ...................................................... 88 Memory Map for H8S/2371 and H8S/2371R (1) ......................................................
Figure 6.16 Figure 6.17 Figure 6.18 Figure 6.19 Figure 6.20 Figure 6.21 Figure 6.22 Figure 6.23 Figure 6.24 Figure 6.25 Figure 6.26 Figure 6.27 Figure 6.28 Figure 6.29 Figure 6.30 Figure 6.31 Figure 6.32 Figure 6.33 Figure 6.34 Figure 6.35 Figure 6.36 Figure 6.37 Figure 6.38 Figure 6.39 Figure 6.40 Figure 6.41 Figure 6.42 Figure 6.43 Figure 6.44 Figure 6.45 Figure 6.46 Figure 6.47 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) ............
Figure 6.48 Example of Write Access Timing when CAS Latency Control Cycle Is Disabled (SDWCD = 1) ......................................................................................................... 227 Figure 6.49 DQMU and DQML Control Timing (Upper Byte Write Access: SDWCD = 0, CAS Latency 2) ................................................................................ 228 Figure 6.50 DQMU and DQML Control Timing (Lower Byte Read Access: CAS Latency 2) .............................................
Figure 6.76 Example of Idle Cycle Operation after DRAM Access (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) .......... 259 Figure 6.77 Example of Idle Cycle Operation after DRAM Access (Write after Read) (IDLC = 0, RAST = 0, CAST = 0)............................................ 260 Figure 6.78 Example of Idle Cycle Operation after DRAM Write Access (IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0) ........................................................ 261 Figure 6.
Figure 7.21 Figure 7.22 Figure 7.23 Figure 7.24 Figure 7.25 Figure 7.26 Figure 7.27 Figure 7.28 Figure 7.29 Figure 7.30 Figure 7.31 Figure 7.32 Figure 7.33 Figure 7.34 Figure 7.35 Figure 7.36 Figure 7.37 Figure 7.38 Figure 7.39 Figure 7.40 Figure 7.41 Example of Full Address Mode Transfer (Block Transfer Mode) .......................... 335 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer................. 336 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer.....
Figure 8.17 Example of Block Transfer Mode (Cycle Steal Mode) Transfer............................. 395 Figure 8.18 Example of Normal Mode Transfer Activated by EDREQ Pin Falling Edge ......... 396 Figure 8.19 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Falling Edge................................................................................... 397 Figure 8.20 Example of Normal Mode Transfer Activated by EDREQ Pin Low Level ..............................................................
Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode (No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0) .............. 413 Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0) ..................... 414 Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1)........................ 415 Figure 8.
Figure 11.11 Example of Synchronous Operation........................................................................ 591 Figure 11.12 Compare Match Buffer Operation........................................................................... 592 Figure 11.13 Input Capture Buffer Operation............................................................................... 592 Figure 11.14 Example of Buffer Operation Setting Procedure..................................................... 593 Figure 11.
Figure 11.52 Contention between Overflow and Counter Clearing ............................................. 627 Figure 11.53 Contention between TCNT Write and Overflow..................................................... 628 Section 12 Programmable Pulse Generator (PPG) ............................................ 631 Figure 12.1 Block Diagram of PPG............................................................................................ 632 Figure 12.2 Overview Diagram of PPG...........................
Figure 15.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits).................................................. 723 Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 725 Figure 15.4 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode). 726 Figure 15.5 Sample SCI Initialization Flowchart ....................................................................... 727 Figure 15.
Figure 15.35 Example of Synchronous Transmission Using DTC............................................... 766 Figure 15.36 Sample Flowchart for Mode Transition during Transmission................................. 768 Figure 15.37 Port Pin States during Mode Transition (Internal Clock, Asynchronous Transmission) ........................................................ 769 Figure 15.38 Port Pin States during Mode Transition (Internal Clock, Synchronous Transmission) ...........................................
Figure 18.2 Block Diagram of D/A Converter for H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R ....................................................................................................... 823 Figure 18.3 Example of D/A Converter Operation..................................................................... 830 Section 20 Flash Memory (0.35-μm F-ZTAT Version) ....................................833 Figure 20.1 Block Diagram of Flash Memory.............................................................
Section 22 Masked ROM .................................................................................. 953 Figure 22.1 Block Diagram of 256-kbyte Masked ROM (HD6432375) .................................... 953 Section 23 Clock Pulse Generator ..................................................................... 955 Figure 23.1 Figure 23.2 Figure 23.3 Figure 23.4 Figure 23.5 Figure 23.6 Figure 23.7 Block Diagram of Clock Pulse Generator ...............................................................
Figure 26.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1)............. 1083 Figure 26.23 External Bus Release Timing ................................................................................ 1084 Figure 26.24 External Bus Request Output Timing.................................................................... 1084 Figure 26.25 Synchronous DRAM Basic Access Timing (CAS Latency 2) .............................. 1085 Figure 26.26 Synchronous DRAM Self-Refresh Timing ...............
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Tables Section 1 Overview................................................................................................1 Table 1.1 Table 1.2 Pin Arrangement in Each Operating Mode ............................................................... 12 Pin Functions............................................................................................................. 18 Section 2 CPU......................................................................................................35 Table 2.
Table 6.2 Table 6.3 Table 6.4 Table 6.5 Table 6.6 Table 6.7 Table 6.8 Table 6.9 Table 6.10 Table 6.11 Table 6.12 Table 6.13 Bus Specifications for Each Area (Basic Bus Interface) ......................................... 173 Data Buses Used and Valid Strobes ........................................................................ 178 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space.............. 191 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing .....
Table 9.6 Table 9.7 Table 9.8 Register Function in Block Transfer Mode ............................................................. 442 DTC Execution Status ............................................................................................. 446 Number of States Required for Each Execution Status ........................................... 446 Section 10 I/O Ports ...........................................................................................455 Table 10.1 Table 10.2 Table 10.
Table 11.29 Table 11.30 Table 11.31 Table 11.32 Table 11.33 Table 11.34 Table 11.35 Table 11.36 Cascaded Combinations .......................................................................................... 596 PWM Output Registers and Output Pins................................................................. 599 Clock Input Pins in Phase Counting Mode.............................................................. 603 Up/Down-Count Conditions in Phase Counting Mode 1 ....................................
Section 16 I2C Bus Interface 2 (IIC2) (Option) .................................................771 Table 16.1 Table 16.2 Table 16.3 Table 16.4 Pin Configuration .................................................................................................... 773 Transfer Rate ........................................................................................................... 776 Interrupt Requests ...................................................................................................
Table 21.8 (2) Useable Area for Erasure in User Program Mode................................................. 914 Table 21.8 (3) Useable Area for Programming in User Boot Mode ............................................. 916 Table 21.8 (4) Useable Area for Erasure in User Boot Mode....................................................... 918 Table 21.9 Hardware Protection................................................................................................ 920 Table 21.10 Software Protection ......
Table 26.20 Table 26.21 Table 26.22 Table 26.23 Table 26.24 Table 26.25 Table 26.26 Table 26.27 Table 26.28 Table 26.29 Table 26.30 Table 26.31 Table 26.32 Table 26.33 Table 26.34 Table 26.35 Table 26.36 Table 26.37 Table 26.38 Table 26.39 Table 26.40 Table 26.41 Appendix Table D.1 Bus Timing (1) ...................................................................................................... 1041 Bus Timing (2) .........................................................................................
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Section 1 Overview Section 1 Overview 1.
Section 1 Overview • On-chip memory ROM Type Model ROM RAM Remarks Flash memory version HD64F2378B 512 kbytes 32 kbytes H8S/2378 0.18μm F-ZTAT Group H8S/2378R 0.18μm F-ZTAT Group Masked ROM version ROMless version HD64F2378R 512 kbytes 32 kbytes HD64F2377 384 kbytes 24 kbytes HD64F2377R 384 kbytes 24 kbytes HD64F2374 384 kbytes 32 kbytes H8S/2378 0.18μm F-ZTAT Group HD64F2374R 384 kbytes 32 kbytes H8S/2378R 0.18μm F-ZTAT Group HD64F2372 256 kbytes 32 kbytes H8S/2378 0.
Section 1 Overview Port A Port B Periheral adree bus PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 Port C DMAC ROM* (Flash memory) PA7/A23/IRQ7 PA6/A22/IRQ6 PA5/A21/IRQ5 PA4/A20/IRQ4 PA3/A19 PA2/A18 PA1/A17 PA0/A16 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 Port 3 DTC Peripheral data bus Port F Port G Interrupt controller Bus controller PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 Internal data bus H8S/2000 CPU Clock pulse generator PG6/BREQ PG5/BACK P
Port A PA7/A23/IRQ7 PA6/A22/IRQ6 PA5/A21/IRQ5 PA4/A20/IRQ4 PA3/A19 PA2/A18 PA1/A17 PA0/A16 Port B PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 Port C PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 Port 3 DMAC ROM* (Flash memory) Periheral adree bus DTC Peripheral data bus Port F Port G Interrupt controller Bus controller PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 Internal data bus H8S/2000 CPU Clock pulse generator PG6/BREQ PG5/BACK PG4/BREQO PG3/CS3/RA
Port A Port B Port 6 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 P35/SCK1/SCL0/(OE)/(CKE)* P34/SCK0/SCK4/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD WDT SCI x 5 channels 2 I C bus interface 2 (option) TPU x 6 channels Port 5 8-bit D/A converter x 2 channels PPG 10-bit A/D converter Port 8 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 Port C RAM PA7/A23/IRQ7 PA6/A22/IRQ6 PA5/A21/IRQ5 PA4/A20/IRQ4 PA3/A19 PA2/A18 PA1/A17 PA0/A16 Port 3 DMAC ROM* (M
Port A Port B Port 6 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 P35/SCK1/SCL0/(OE)/(CKE)* P34/SCK0/SCK4/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD WDT SCI x 5 channels I2 C bus interface (option) TPU x 6 channels Port 5 8-bit D/A converter x 2 channels PPG 10-bit A/D converter Port 8 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 Port C RAM PA7/A23/IRQ7 PA6/A22/IRQ6 PA5/A21/IRQ5 PA4/A20/IRQ4 PA3/A19 PA2/A18 PA1/A17 PA0/A16 Port 3 DMAC Periheral
Section 1 Overview Pin Description 1.3.
LQFP-144 (Top view) 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Vcc PE7/D7 Vss PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 DCTL P85/(IRQ5)/SCK3/EDACK3 P84/(IRQ4)/EDACK2 P83/(IRQ3)/RxD3/ETEND3 P27/
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 LQFP-144 (Top view) 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 Vcc PE7/D7 Vss PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 DCTL P85/(IRQ5)/SCK3 P84/(IRQ4) P83/(IRQ3)/RxD3 P27/PO7/TIOCB5/(IRQ15) P26/PO6/TIOCA5/(IRQ14) P25/PO5/TIOCB4/(IRQ13) P24/PO4/TIOCA4/RxD4/(IRQ12) P23/PO3/TIOCD3/TxD4/(IRQ11)
LQFP-144 (Top view) 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Vcc PE7/D7 Vss PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 DCTL*4 P85/(IRQ5)/SCK3 P84/(IRQ4) P83/(IRQ3)/RxD3 P27/PO7/TIOCB5/(IRQ15)
Section 1 Overview 1 2 3 4 5 A VSS MD1 MD0 P32 P35 B MD2 VCC P31 P34 P51 C PC0 P80 PC1 P30 D PC4 PC2 PC3 E PC7 VSS F PB3 G 9 10 11 12 13 P50 AVSS P94 P90 P44 P40 PG2 PG3 PG4 P93 P47 P45 P42 AVCC VREF PG1 P33 P52 PG5 P92 P46 P43 P41 P64 P53 PG6 P97 P96 P95 P91 P63 PG0 VCC STBY PC5 PB0 NC VSS VSS NC EXTAL PC6 PB1 VSS PF7 VCC RES XTAL PB6 PB2 PA0 PB4 PF6 NC PF5 PLLVSS H VSS PB7 PA3 PB5 PF2 PF4 PF1 PLLVCC J PA5 PA2 PA
Section 1 Overview 1.3.2 Pin Arrangement in Each Operating Mode Table 1.1 Pin Arrangement in Each Operating Mode Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview 1.3.3 Table 1.2 Pin Functions Pin Functions Pin No. H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group (LQFP-144) H8S/2378 0.18μm F-ZTAT Group, H8S/2378R H8S/2375 0.18μm H8S/2373 F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R I/O Type Symbol Power supply VCC 4, 41, 72, 98, 99 B2, N12, F11, D12 4, 41, 72, 98, 99 VSS 2, 10, 18, 25, 50, 70, 95, 102 A1, E2, F4, H1, K5, L10, E10, E11 PLLVCC 91 PLLVSS VCL*3 Input For connection to the power supply.
Section 1 Overview Pin No. H8S/2378 0.18μm F-ZTAT Group, H8S/2375 H8S/2378R H8S/2373 0.18μm F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R I/O Type Symbol H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group (LQFP-144) Clock XTAL 96 F13 96 96 Input For connection to a crystal oscillator. See section 23, Clock Pulse Generator, for typical connection diagrams for a crystal resonator and external clock input.
Section 1 Overview Pin No. Type Symbol Operating MD2 mode MD1 control MD0 DCTL*1 H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group (LQFP-144) H8S/2378 0.18μm F-ZTAT Group, H8S/2375 H8S/2378R H8S/2373 0.18μm F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R I/O 1, 144, 143 B1, A2, A3 1, 144, 143 1, 144, 143 Input These pins set the operating mode. These pins should not be changed while the MCU is operating.
Section 1 Overview Pin No. Type Symbol H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group (LQFP-144) System control EMLE 32 H8S/2378 0.18μm F-ZTAT Group, H8S/2375 H8S/2378R H8S/2373 0.18μm F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R I/O K1 32 32 Input Function On-chip Emulator Enable Pin When the on-chip emulator in the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2377R, or H8S/2378R 0.18μm F-ZTAT Group is used, this pin should be fixed high.
Section 1 Overview Pin No. H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group (LQFP-144) H8S/2378 0.18μm F-ZTAT Group, H8S/2375 H8S/2378R H8S/2373 0.
Section 1 Overview Pin No. Type Symbol H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group (LQFP-144) Bus control HWR 88 H8S/2378 0.18μm F-ZTAT Group, H8S/2375 H8S/2378R H8S/2373 0.18μm F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R I/O H11 88 88 Function Output Strobe signal indicating that external address space is to be written, and the upper half (D15 to D8) of the data bus is enabled. Write enable signal for accessing the DRAM space.
Section 1 Overview Pin No. Type Symbol H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group (LQFP-144) Bus control UCAS 85 H8S/2378 0.18μm F-ZTAT Group, H8S/2375 H8S/2378R H8S/2373 0.18μm F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R I/O H12 85 85 Function Output Upper column address strobe signal for accessing the 16-bit DRAM space. Column address strobe signal for accessing the 8-bit DRAM space.
Section 1 Overview Pin No. Type Symbol Bus control RAS/ RAS2 RAS3 to RAS5 H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group (LQFP-144) H8S/2378 0.18μm F-ZTAT Group, H8S/2375 H8S/2378R H8S/2373 0.18μm F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R I/O 109, 110, 35, 36 A12, A13, L1, M1 109, 110, 35, 36 109, 110, 35, 36 Function Output Row address strobe signal for the synchronous DRAM interface.
Section 1 Overview Pin No. Type Symbol H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group (LQFP-144) Bus control OE (OE) 38, 137 H8S/2378 0.18μm F-ZTAT Group, H8S/2375 H8S/2378R H8S/2373 0.18μm F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R I/O M2, A5 38, 137 38, 137 Function Output Output enable signal for DRAM interface space. The output pins of OE and (OE) are selected by the port function control register 2 (PFCR2) of port 3.
Section 1 Overview Pin No. H8S/2378 0.18μm F-ZTAT Group, H8S/2375 H8S/2378R H8S/2373 0.18μm F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R I/O Type Symbol H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group (LQFP-144) DMA controller (DMAC) DREQ1 DREQ0 82, 81 K13, J12 82, 81 82, 81 Input TEND1 TEND0 104, 83 D10, J10 104, 83 104, 83 Output These signals indicate the end of DMAC data transfer.
Section 1 Overview Pin No. Type H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group (LQFP-144) H8S/2378 0.18μm F-ZTAT Group, H8S/2375 H8S/2378R H8S/2373 0.18μm F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R I/O 44, 45, 47, 49 L4, N4, L5, N5 44, 45, 47, 49 44, 45, 47, 49 Input TIOCA0 TIOCB0 TIOCC0 TIOCD0 42, 43, 44, 45 L3, M4, L4, N4 42, 43, 44, 45 42, 43, 44, 45 Input/ TGRA_0 to output TGRD_0 input capture input/output compare output/ PWM output pins.
Section 1 Overview Pin No. H8S/2378 0.18μm F-ZTAT Group, H8S/2375 H8S/2378R H8S/2373 0.18μm F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R I/O Type Symbol H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group (LQFP-144) Programmable pulse generator (PPG) PO15 to PO0 49 to 42, 58 to 51 N5, M6, L5, M5, N4, L4, M4, L3, M8, N7, K8, K7, K6, N6, M7, L6 49 to 42, 58 to 51 49 to 42, 58 to 51 Output Pulse output pins.
Section 1 Overview Pin No. Type H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group (LQFP-144) H8S/2378 0.18μm F-ZTAT Group, H8S/2375 H8S/2378R H8S/2373 0.18μm F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R I/O 139, 137 C5, A5 139, 137 139, 137 Input/ I2C clock input/ output output pins. 140, 138 A4, B4 140, 138 140, 138 Input/ I2C data input/ output output pins.
Section 1 Overview Pin No. Type Symbol AVCC A/D converter, D/A converter H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group (LQFP-144) H8S/2378 0.18μm F-ZTAT Group, H8S/2375 H8S/2378R H8S/2373 0.18μm F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R I/O 111 B11 111 111 Input Function The analog powersupply pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+3 V).
Section 1 Overview Pin No. H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group (LQFP-144) H8S/2378 0.18μm F-ZTAT Group, H8S/2375 H8S/2378R H8S/2373 0.18μm F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R I/O Function Type Symbol I/O ports P17 to P10 49 to 42 N5, M6, L5, M5, N4, L4, M4, L3 49 to 42 49 to 42 Input/ Eight-bit input/ output output pins. P27 to P20 58 to 51 M8, N7, K8, K7, K6, N6, M7, L6 58 to 51 58 to 51 Input/ Eight-bit input/ output output pins.
Section 1 Overview Pin No. H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.18μm F-ZTAT Group (LQFP-144) H8S/2378 0.18μm F-ZTAT Group, H8S/2375 H8S/2378R H8S/2373 0.18μm F-ZTAT Group H8S/2377 H8S/2375R (LGA-145) H8S/2377R H8S/2373R I/O Function Type Symbol I/O ports PD7 to PD0 80 to 73 K11, K12, L13, L11, M12, L12, N13, M13 80 to 73 80 to 73 Input/ Eight-bit input/ output output pins.
Section 1 Overview Rev.7.00 Mar.
Section 2 CPU Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. 2.
Section 2 CPU ⎯ 16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W) ⎯ 32 ÷ 16-bit register-register divide: 20 states (DIVXU.W) • Two CPU operating modes ⎯ Normal mode* ⎯ Advanced mode Note: * For this LSI, normal mode is not available. • Power-down state ⎯ Transition to power-down state by SLEEP instruction ⎯ Selectable CPU clock speed 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
Section 2 CPU 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers ⎯ Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added. • Expanded address space ⎯ Normal mode supports the same 64-kbyte address space as the H8/300 CPU. ⎯ Advanced mode supports a maximum 16-Mbyte address space.
Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI’s mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU in normal mode. • Address space Linear access to a maximum address space of 64 kbytes is possible.
Section 2 CPU • Stack structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling. Note: For this LSI, normal mode is not available.
Section 2 CPU 2.2.2 Advanced Mode • Address space Linear access to a maximum address space of 16 Mbytes is possible. • Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the upper 16-bit segments of 32-bit registers or address registers. • Instruction set All instructions and addressing modes can be used.
Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.
Section 2 CPU 2.4 Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR).
Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR) EXR is an 8-bit register that can be operated by the LDC, STC, ANDC, ORC, and XORC instructions.
Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.
Section 2 CPU Bit Bit Name Initial Value R/W Description 1 V Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: • Add instructions, to indicate a carry • Subtract instructions, to indicate a borrow • Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.
Section 2 CPU 2.5.1 General Register Data Formats Figure 2.9 shows the data formats of general registers. Data Type Register Number Data Format 7 RnH 1-bit data 0 Don't care 7 6 5 4 3 2 1 0 7 1-bit data RnL 4-bit BCD data RnH 4-bit BCD data RnL Byte data RnH Don't care 7 4 3 Upper 0 7 6 5 4 3 2 1 0 0 Lower Don't care 7 Don't care 7 4 3 Upper 0 Don't care MSB LSB 7 Byte data RnL 0 Don't care MSB Figure 2.9 General Register Data Formats (1) Rev.7.00 Mar.
Section 2 CPU Data Type Register Number Word data Rn Data Format 15 0 MSB Word data 15 0 MSB Longword data LSB En LSB ERn 31 16 15 MSB En 0 Rn LSB Legend: ERn En Rn RnH RnL MSB LSB : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.9 General Register Data Formats (2) Rev.7.00 Mar.
Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
Section 2 CPU 2.6 Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.
Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.
Section 2 CPU Table 2.3 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI. MOVTPE B Cannot be used in this LSI. POP W/L @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.
Section 2 CPU Table 2.4 Arithmetic Operations Instructions Instruction Size* Function ADD B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd 1 SUB ADDX Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes. Use the SUBX or ADD instruction.
Section 2 CPU 1 Instruction Size* Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets the CCR bits according to the result.
Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
Section 2 CPU Table 2.7 Bit Manipulation Instructions Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ∼ (
Section 2 CPU Instruction Size* Function BXOR B C ⊕ ( of ) → C Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ∼ ( of ) → C Logically exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (
Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Table 2.9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves the memory operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.
Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next: EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next: Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. 2.6.
Section 2 CPU (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc. Figure 2.11 Instruction Formats (Examples) 2.
Section 2 CPU Table 2.11 Addressing Modes No. Addressing Mode Symbol 1 Register direct Rn 2 Register indirect @ERn 3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn) 4 Register indirect with post-increment @ERn+ Register indirect with pre-decrement @–ERn 5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 Immediate #xx:8/#xx:16/#xx:32 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 8 Memory indirect @@aa:8 2.7.
Section 2 CPU Register Indirect with Pre-Decrement—@-ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, and 4 for longword access. For word or longword transfer instructions, the register value should be even. 2.7.
Section 2 CPU 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-extended to 24 bits and added to the 24-bit address indicated by the PC value to generate a 24-bit branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00).
Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table 2.13 Effective Address Calculation No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct (Rn) rm Operand is general register contents.
Section 2 CPU No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 31 op @aa:16 31 op 0 H'FFFF 24 23 16 15 0 Don't care Sign extension abs @aa:24 31 op 8 7 24 23 Don't care abs 24 23 0 Don't care abs @aa:32 op 31 6 Immediate #xx:8/#xx:16/#xx:32 op 7 0 24 23 Don't care abs Operand is immediate data.
Section 2 CPU 2.8 Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset state In this state the CPU and internal peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state.
Section 2 CPU End of bus request Bus request En d En d of Re ex qu ce es pt tf ion or ha ex nd ce lin pt g ion ha nd lin g Sleep mode st que t re up terr =0 BY SS EEP tion SL truc ins Bus-released state ion = 1 ruct BY nst SS EP i E SL of bu s re Bu qu sr es eq t ue st Program execution state In Exception handling state External interrupt request Software standby mode RES = High Reset state*1 STBY = High, RES = Low Hardware standby mode*2 Reset state Power down state*3 Notes: 1.
Section 2 CPU Rev.7.00 Mar.
Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection The H8S/2378 0.18μm F-ZTAT Group and H8S/2378R 0.18μm F-ZTAT Group have six operating modes (modes 1 to 5 and 7). The H8S/2377 and H8S/2377R have five operating modes (modes 1 to 4 and 7). The H8S/2375 and H8S/2375R has four operating modes (modes 1, 2, 4, and 7). The H8S/2373 and H8S/2373R has two operating modes (modes 1 and 2). The operating mode is selected by the setting of mode pins (MD2 to MD0).
Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode of this LSI. Bit Bit Name Initial Value R/W Descriptions 7 to 3 ⎯ All 0 ⎯ Reserved 2 1 0 MDS2 MDS1 MDS0 Note: 3.2.2 These bits are always read as 0 and cannot be modified.
Section 3 MCU Operating Modes • H8S/2378 0.18μm F-ZTAT Group and H8S/2378R 0.18μm F-ZTAT Group Bit Bit Name Initial Value R/W Descriptions 7, 6 ⎯ All 1 R/W Reserved 5, 4 ⎯ All 0 R/W The initial value should not be modified. Reserved The initial value should not be modified. 3 FLSHE 0 R/W Flash Memory Control Register Enable Controls CPU access to the flash memory control registers. If this bit is set to 1, the flash memory control registers can be read from and written to.
Section 3 MCU Operating Modes • H8S/2377, H8S/2377R, H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R Bit Bit Name Initial Value R/W Descriptions 7, 6 ⎯ All 1 R/W Reserved 5, 4 ⎯ All 0 R/W The initial value should not be modified. Reserved The initial value should not be modified. 3 FLSHE 0 R/W Flash Memory Control Register Enable Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2).
Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C function as an address bus, ports D and E function as a data bus, and parts of ports F and G carry bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, if 8-bit access is designated for all areas by the bus controller, the bus mode switches to 8 bits. 3.3.
Section 3 MCU Operating Modes In the flash memory version, user program mode is entered by setting the SWE bit of FLMCR1 to 1. 3.3.5 Mode 5 This mode is a user boot mode of the flash memory. This mode is the same as mode 7, except for the programming and erasure on the flash memory. Mode 5 is only available in the H8S/2378 0.18μm F-ZTAT Group and H8S/2378R 0.18μm F-ZTAT Group. 3.3.6 Mode 7 The CPU can access a 16-Mbyte address space in advanced mode.
Section 3 MCU Operating Modes 3.3.7 Pin Functions Table 3.2 shows the pin functions in each operating mode. Table 3.
Section 3 MCU Operating Modes 3.4 Memory Map in Each Operating Mode Figures 3.1 to 3.17 show memory maps for each product.
Section 3 MCU Operating Modes ROM: 512 kbytes RAM: 32 kbytes Mode 5 (User boot mode) ROM: 512 kbytes RAM: 32 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'080000 H'FF4000 H'FFD000 External address space H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF H'080000 External address space/ reserved area*2*4 On-chip RAM/ external address space*1 Reserved area*4 Internal I/O registers External address space Internal I/O registers On-chip ROM On-chip ROM External address sp
Section 3 MCU Operating Modes RAM: 24 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 ROM: 384 kbytes RAM: 24 kbytes Mode 3 (Boot mode) H'000000 On-chip ROM External address space H'060000 External address space/ Reserved area*2*4 H'FF4000 H'FF6000 H'FFC000 Reserved area*4 On-chip RAM/ external address space*1 Reserved area*4 H'FF4000 H'FF6000 Reserved area*4 On-chip RAM*3 H'FFC000 Reserved area*4 H'FFC800 External address space H'FFC800 H'FFFC00 Internal I/O regist
Section 3 MCU Operating Modes ROM: 384 kbytes RAM: 24 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) ROM: 384 kbytes RAM: 24 kbytes Mode 7 (Single-chip activation expanded mode, with on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'060000 On-chip ROM H'060000 External address space/ reserved area*2*4 External address space H'FF4000 H'FF6000 H'FFC000 Reserved area*4 On-chip RAM/ external address space*1 Reserved area*4 H'FFC800 External address space H'FFFC00 H'FFFF00 H'FFFF20 H'FFFF
Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 16 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) RAM: 16 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 H'000000 On-chip ROM H'040000 External address space Reserved area*2 H'060000 External address space H'FF4000 H'FF8000 H'FFC000 H'FFC800 H'FFFC00 Reserved area*2 On-chip RAM/ external address space*1 Reserved area*2 H'FF4000 H'FF8000 H'FFC000 Reserved area*2 On-chip RAM/ external address space*1 Reserved are
Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 16 kbytes Mode 7 (Single-chip activation expanded mode, with on-chip ROM enabled) H'000000 On-chip ROM H'040000 Reserved area*3 H'060000 External address space/ reserved area*1*3 H'FF4000 H'FF8000 Reserved area*3 On-chip RAM/ external address space*2 H'FFC000 H'FFC800 Reserved area*3 External address space/ reserved area*1*3 H'FFFC00 Internal I/O registers H'FFFF00 External address space/ reserved area*1*3 H'FFFF20 Internal I/O registers H'FFFFFF
Section 3 MCU Operating Modes RAM: 32 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 ROM: 384 kbytes RAM: 32 kbytes Mode 3 (Boot mode) H'000000 On-chip ROM H'060000 Reserved area*4 External address space H'080000 External address space/ reserved area*2*4 H'FF4000 H'FF4000 On-chip RAM/ external address space*1 H'FFC000 Reserved area*4 On-chip RAM*3 H'FFC000 H'FFD000 External address space H'FFD000 H'FFFC00 Internal I/O registers H'FFFC00 H'FFFF00 External address s
Section 3 MCU Operating Modes ROM: 384 kbytes RAM: 32 kbytes Mode 5 (User boot mode) ROM: 384 kbytes RAM: 32 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'060000 Reserved area*4 H'080000 On-chip ROM H'060000 Reserved area*4 H'FFD000 External address space H'FFFF00 H'FFFF20 H'FFFFFF Internal I/O registers External address space Internal I/O registers H'060000 External address space/ reserved area*2*4 H'FF4000 On-chip H'FFC000 Reserved area*4 H'0800
Section 3 MCU Operating Modes RAM: 16 kbytes Modes 1 and 2 Expanded mode with on-chip ROM disabled H'000000 External address space H'FF4000 H'FF8000 Reserved area*2 On-chip external address space*1 H'FFC000 H'FFC800 Reserved area*2 External address space H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF Internal I/O register External address space Internal I/O register Notes: 1. This area is specified as external address space by clearing the RAME bit in SYSCR to 0. 2. A reserved area should not be accessed.
Section 3 MCU Operating Modes RAM: 32 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 ROM: 256 kbytes RAM: 32 kbytes Mode 3 (Boot mode) H'000000 On-chip ROM H'040000 Reserved area*4 External address space H'080000 External address space/ reserved area*2*4 H'FF4000 H'FF4000 On-chip RAM/ external address space*1 H'FFC000 Reserved area*4 On-chip RAM*3 H'FFC000 H'FFD000 External address space H'FFD000 H'FFFC00 Internal I/O registers H'FFFC00 H'FFFF00 External address s
Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 32 kbytes Mode 5 (User boot mode) ROM: 256 kbytes RAM: 32 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'040000 On-chip ROM Reserved area*4 H'FFD000 External address space H'FFFF00 H'FFFF20 H'FFFFFF H'080000 H'FF4000 Reserved area*4 Internal I/O registers External address space Internal I/O registers Reserved area*4 External address space/ reserved area*2*4 On-chip RAM/ external address space*1 H'FFF
Section 3 MCU Operating Modes RAM: 24 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 ROM: 256 kbytes RAM: 24 kbytes Mode 3 (Boot mode) H'000000 On-chip ROM H'040000 Reserved area*4 External address space H'080000 External address space/ reserved area*2*4 H'FF4000 H'FF6000 H'FFC000 H'FFD000 H'FFFC00 Reserved area*4 On-chip RAM/ external address space*1 Reserved area*4 H'FF4000 H'FF6000 Reserved area*4 On-chip RAM*3 H'FFC000 Reserved area*4 External address space H'FFD0
Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 24 kbytes Mode 5 (User boot mode) ROM: 256 kbytes RAM: 24 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'040000 On-chip ROM Reserved area*4 Reserved area*4 H'FF4000 On-chip RAM/ external address space*1 Reserved area*4 H'FF6000 H'FFFF00 H'FFFF20 H'FFFFFF External address space Internal I/O registers External address space Internal I/O registers Reserved area*4 H'080000 External address space/ reserved
Section 3 MCU Operating Modes RAM: 16 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 ROM: 256 kbytes RAM: 16 kbytes Mode 3 (Boot mode) H'000000 On-chip ROM H'040000 Reserved area*4 External address space H'080000 External address space/ reserved area*2*4 H'FF4000 H'FF8000 H'FFC000 H'FFD000 H'FFFC00 Reserved area*4 On-chip RAM/ external address space*1 Reserved area*4 H'FF4000 H'FF8000 Reserved area*4 On-chip RAM*3 H'FFC000 Reserved area*4 External address space H'FFD0
Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 16 kbytes Mode 5 (User boot mode) ROM: 256 kbytes RAM: 16 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 H'000000 H'040000 H'080000 Reserved area*4 H'FF4000 H'FF8000 On-chip RAM/ external address space*1 Reserved area*4 H'FF8000 H'FFFF00 H'FFFF20 H'FFFFFF External address space Internal I/O registers External address space Internal I/O registers Reserved area*4 H'080000 External address space/ reserved area*2*4 H'FF4000 H'
Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode.
Section 4 Exception Handling Table 4.
Section 4 Exception Handling 1 Vector Address* External interrupt 4 Internal interrupt* Notes: 1. 2. 3. 4. 4.3 2 Vector Number Normal Mode* Advanced Mode IRQ13 29 H'003A to H'003B H'0074 to H'0077 IRQ14 30 H'003C to H'003D H'0078 to H'007B IRQ15 31 H'003E to H'003F H'007C to H'007F 32 ⎜ 118 H'0040 to H'0041 ⎜ H'00EC to H'00ED H'0080 to H'0083 ⎜ H'01D8 to H'01DB Exception Source Lower 16 bits of the address. Not available in this LSI. Not available in this LSI.
Section 4 Exception Handling Vector fetch Prefetch of first Internal processing program instruction (1) (3) φ RES Internal address bus (5) Internal read signal Internal write signal Internal data bus High (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Figure 4.
Section 4 Exception Handling Internal processing Vector fetch * φ * Prefetch of first program instruction * RES Address bus (1) (3) (5) RD HWR, LWR D15 to D0 High (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * Seven program wait states are inserted. Figure 4.
Section 4 Exception Handling 4.4 Trace Exception Handling Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.
Section 4 Exception Handling 4.6 Trap Instruction Exception Handling Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3.
Section 4 Exception Handling 4.7 Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes*2 SP EXR Reserved*1 SP CCR CCR CCR*1 CCR*1 PC (16 bits) PC (16 bits) Interrupt control mode 0 Interrupt control mode 2 (b) Advanced Modes SP EXR Reserved*1 SP CCR PC (24 bits) Interrupt control mode 0 CCR PC (24 bits) Interrupt control mode 2 Notes: 1. Ignored on return. 2.
Section 4 Exception Handling 4.8 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.
Section 4 Exception Handling Rev.7.00 Mar.
Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). • Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times.
Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1.
Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name I/O Function NMI Input Nonmaskable external interrupt IRQ15 to IRQ0 Input Rising or falling edge can be selected. Maskable external interrupts Rising, falling, or both edges, or level sensing, can be selected. 5.3 Register Descriptions The interrupt controller has the following registers.
Section 5 Interrupt Controller 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Bit Name Initial Value R/W Description 7, 6 — All 0 — Reserved These bits are always read as 0 and the initial value should not be changed. 5 4 INTM1 INTM0 0 0 R/W R/W Interrupt Control Select Mode 1 and 0 These bits select either of two interrupt control modes for the interrupt controller.
Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 15 — 0 — Reserved This bit is always read as 0 and the initial value should not be changed. 14 13 12 IPR14 IPR13 IPR12 1 1 1 R/W R/W R/W Sets the priority of the corresponding interrupt source.
Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 3 — 0 — Reserved This bit is always read as 0 and the initial value should not be changed. 2 1 0 IPR2 IPR1 IPR0 1 1 1 R/W R/W R/W Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) 5.3.
Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 10 IRQ10E 0 R/W IRQ10 Enable The IRQ10 interrupt request is enabled when this bit is 1. 9 IRQ9E 0 R/W IRQ9 Enable The IRQ9 interrupt request is enabled when this bit is 1. 8 IRQ8E 0 R/W IRQ8 Enable The IRQ8 interrupt request is enabled when this bit is 1. 7 IRQ7E 0 R/W IRQ7 Enable The IRQ7 interrupt request is enabled when this bit is 1.
Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCR select the source that generates an interrupt request at pins IRQ15 to IRQ0.
Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 9 8 IRQ12SCB IRQ12SCA 0 0 R/W R/W IRQ12 Sense Control B IRQ12 Sense Control A 00: Interrupt request generated at IRQ12 input low level 01: Interrupt request generated at falling edge of IRQ12 input 10: Interrupt request generated at rising edge of IRQ12 input 11: Interrupt request generated at both falling and rising edges of IRQ12 input 7 6 IRQ11SCB IRQ11SCA 0 0 R/W R/W IRQ11 Sense Control B IRQ11 Sense Control A 00: In
Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 3 2 IRQ9SCB IRQ9SCA 0 0 R/W R/W IRQ9 Sense Control B IRQ9 Sense Control A 00: Interrupt request generated at IRQ9 input low level 01: Interrupt request generated at falling edge of IRQ9 input 10: Interrupt request generated at rising edge of IRQ9 input 11: Interrupt request generated at both falling and rising edges of IRQ9 input 1 0 IRQ8SCB IRQ8SCA 0 0 R/W R/W IRQ8 Sense Control B IRQ8 Sense Control A 00: Interrupt requ
Section 5 Interrupt Controller • ISCRL Bit Bit Name Initial Value R/W Description 15 14 IRQ7SCB IRQ7SCA 0 0 R/W R/W IRQ7 Sense Control B IRQ7 Sense Control A 00: Interrupt request generated at IRQ7 input low level 01: Interrupt request generated at falling edge of IRQ7 input 10: Interrupt request generated at rising edge of IRQ7 input 11: Interrupt request generated at both falling and rising edges of IRQ7 input 13 12 IRQ6SCB IRQ6SCA 0 0 R/W R/W IRQ6 Sense Control B IRQ6 Sense Control A 00: I
Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 9 8 IRQ4SCB IRQ4SCA 0 0 R/W R/W IRQ4 Sense Control B IRQ4 Sense Control A 00: Interrupt request generated at IRQ4 input low level 01: Interrupt request generated at falling edge of IRQ4 input 10: Interrupt request generated at rising edge of IRQ4 input 11: Interrupt request generated at both falling and rising edges of IRQ4 input 7 6 IRQ3SCB IRQ3SCA 0 0 R/W R/W IRQ3 Sense Control B IRQ3 Sense Control A 00: Interrupt requ
Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 3 2 IRQ1SCB IRQ1SCA 0 0 R/W R/W IRQ1 Sense Control B IRQ1 Sense Control A 00: Interrupt request generated at IRQ1 input low level 01: Interrupt request generated at falling edge of IRQ1 input 10: Interrupt request generated at rising edge of IRQ1 input 11: Interrupt request generated at both falling and rising edges of IRQ1 input 1 0 IRQ0SCB IRQ0SCA 0 0 R/W R/W IRQ0 Sense Control B IRQ0 Sense Control A 00: Interrupt requ
Section 5 Interrupt Controller 5.3.5 IRQ Status Register (ISR) ISR is an IRQ15 to IRQ0 interrupt request flag register.
Section 5 Interrupt Controller 5.3.6 IRQ Pin Select Register (ITSR) ITSR selects input pins IRQ15 to IRQ0. Bit Bit Name Initial Value R/W 15 ITS15 0 R/W Description Selects IRQ15 input pin. 0: PF2 1: P27 14 ITS14 0 R/W Selects IRQ14 input pin. 0: PF1 1: P26 13 ITS13 0 R/W Selects IRQ13 input pin. 0: P65 1: P25 12 ITS12 0 R/W Selects IRQ12 input pin. 0: P64 1: P24 11 ITS11 0 R/W Selects IRQ11 input pin. 0: P63 1: P23 10 ITS10 0 R/W Selects IRQ10 input pin.
Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 6 ITS6 0 R/W Selects IRQ6 input pin. 0: PA6 1: PH2 5 ITS5 0 R/W Selects IRQ5 input pin. 0: PA5 1: P85 4 ITS4 0 R/W Selects IRQ4 input pin. 0: PA4 1: P84 3 ITS3 0 R/W Selects IRQ3 input pin. 0: P53 1: P83 2 ITS2 0 R/W Selects IRQ2 input pin. 0: P52 1: P82 1 ITS1 0 R/W Selects IRQ1 input pin. 0: P51 1: P81 0 ITS0 0 R/W Selects IRQ0 input pin. 0: P50 1: P80 Rev.7.00 Mar.
Section 5 Interrupt Controller 5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects the IRQ pins used to recover from the software standby state.
Section 5 Interrupt Controller 5.4 Interrupt Sources 5.4.1 External Interrupts There are seventeen external interrupts: NMI and IRQ15 to IRQ0. These interrupts can be used to restore the chip from software standby mode. NMI Interrupt: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits.
Section 5 Interrupt Controller IRQnE IRQnSCA, IRQnSCB IRQnF Edge/ level detection circuit IRQn input S Q IRQn interrupt request R Clear signal Note: n = 15 to 0 Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 5.4.
Section 5 Interrupt Controller Table 5.
Section 5 Interrupt Controller Vector Address*1 Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority TPU_0 TGI0A 40 H'00A0 IPRF6 to IPRF4 High TGI0B 41 H'00A4 ⎯ TGI0C 42 H'00A8 ⎯ TGI0D 43 H'00AC TCI0V 44 H'00B0 ⎯ ⎯ Reserved for system use 45 H'00B4 ⎯ ⎯ 46 H'00B8 ⎯ ⎯ 47 H'00BC ⎯ ⎯ TPU_1 TPU_2 TPU_3 DTC DMAC Activation Activation ⎯ IPRF6 to IPRF4 TGI1A 48 H'00C0 TGI1B 49 H'00C4 IPRF2 to IPRF0 TCI1V 50 H'00C8 ⎯ ⎯ TCI1U
Section 5 Interrupt Controller Vector Address*1 Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority TPU_4 TGI4A 64 H'0100 IPRG6 to IPRG4 High TGI4B 65 H'0104 TCI4V 66 H'0108 ⎯ ⎯ TCI4U 67 H'010C ⎯ ⎯ TGI5A 68 H'0110 TGI5B 69 H'0114 TCI5V 70 H'0118 ⎯ ⎯ ⎯ ⎯ TPU_5 DTC DMAC Activation Activation ⎯ IPRG2 to IPRG0 ⎯ TCI5U 71 H'011C CMIA0 72 H'0120 CMIB0 73 H'0124 OVI0 74 H'0128 Reserved for system use 75 H'012C IPRH14 to IPRH
Section 5 Interrupt Controller Vector Address*1 Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority DTC DMAC Activation Activation SCI_0 ERI0 88 H'0160 IPRI2 to IPRI0 High ⎯ ⎯ RXI0 89 H'0164 TXI0 90 H'0168 TEI0 91 H'016C ⎯ ⎯ ERI1 92 H'0170 ⎯ ⎯ RXI1 93 H'0174 TXI1 94 H'0178 TEI1 95 H'017C ⎯ ⎯ ERI2 96 H'0180 ⎯ ⎯ RXI2 97 H'0184 ⎯ TXI2 98 H'0188 ⎯ TEI2 99 H'018C ERI3 100 H'0190 RXI3 101 H'0194 TXI3 102 H'0198 SC
Section 5 Interrupt Controller Vector Address*1 Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority DTC DMAC Activation Activation IIC2 IICI0 116 H'01D0 IPRK6 to IPRK4 High ⎯ ⎯ Reserved for system use 117 H'01D4 ⎯ ⎯ IICI1 118 H'01D8 ⎯ ⎯ Reserved for system use 119 H'01DC ⎯ ⎯ Reserved for system use 120 H'01E0 ⎯ ⎯ 121 H'01E4 ⎯ ⎯ 122 H'01E8 ⎯ ⎯ 123 H'01EC ⎯ ⎯ 124 H'01F0 ⎯ ⎯ 125 H'01F4 ⎯ ⎯ 126 H'01F8 127 H'01EC IPRK2 t
Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.
Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program execution status No Interrupt generated? Yes Yes NMI No I=0 No Hold pending Yes No IRQ0 No Yes IRQ1 Yes IICI1 Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.
Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2.
Section 5 Interrupt Controller Program execution status Interrupt generated? No Yes Yes NMI No Level 7 interrupt? No Yes Mask level 6 or below? Level 6 interrupt? No No Yes Level 1 interrupt? Yes Mask level 5 or below? No No Yes Yes Mask level 0? No Yes Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 5.6.
(1) (2) (4) (3) Internal operation Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.
Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.
Section 5 Interrupt Controller Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus 16 Bit Bus Symbol Internal Memory 2-State Access 3-State Access 2-State Access 3-State Access Instruction fetch SI 1 4 6+2m 2 3+m Branch address read SJ Stack manipulation SK Legend: m: Number of wait states in an external device access. 5.6.5 DTC and DMAC Activation by Interrupt The DTC and DMAC can be activated by an interrupt.
Section 5 Interrupt Controller 5.7 Usage Notes 5.7.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective after execution of the instruction.
Section 5 Interrupt Controller 5.7.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.
Section 5 Interrupt Controller 5.7.6 IRQ Status Register (ISR) Depending on the pin status following a reset, IRQnF may be set to 1. Therefore, always read ISR and clear it to 0 after resets. Rev.7.00 Mar.
Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the bus mastership⎯the CPU, DMA controller (DMAC), EXDMA controller (EXDMAC)*, and data transfer controller (DTC). A block diagram of the bus controller is shown in figure 6.1.
Section 6 Bus Controller (BSC) EXDMAC address bus Internal address bus Address selector CS7 to CS0 Area decoder WAIT BREQ BACK BREQO External bus controller Internal bus master bus request signal EXDMAC bus request signal Internal bus master bus acknowledge signal EXDMAC bus acknowledge signal External bus arbiter External bus control signals Internal bus control signals Internal bus controller CPU bus request signal DTC bus request signal DMAC bus request signal CPU bus acknowledge signal DTC bus
Section 6 Bus Controller (BSC) 6.2 Input/Output Pins Table 6.1 shows the pin configuration of the bus controller. Table 6.1 Pin Configuration Name Symbol I/O Function Address strobe AS Output Strobe signal indicating that normal space is accessed and address output on address bus is enabled. Read RD Output Strobe signal indicating that normal space is being read.
Section 6 Bus Controller (BSC) Name Symbol I/O Function Chip select 4/ row address strobe 4/ 1 write enable* CS4/ RAS4/ 1 WE* Output Strobe signal indicating that area 4 is selected, DRAM row address strobe signal when area 4 is DRAM space, or write enable signal of the synchronous DRAM when the synchronous DRAM interface is selected.
Section 6 Bus Controller (BSC) Name Symbol I/O Function Data transfer acknowledge 1 (DMAC) DACK1 Output Data transfer acknowledge signal for single address transfer by DMAC channel 1. Data transfer acknowledge 0 (DMAC) DACK0 DACK0 Data transfer acknowledge signal for single address transfer by DMAC channel 0. EDACK3* Output Data transfer acknowledge signal for single address transfer by EXDMAC channel 3.
Section 6 Bus Controller (BSC) 6.3 Register Descriptions The bus controller has the following registers.
Section 6 Bus Controller (BSC) 6.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area in the external address space as either 8-bit access space or 16-bit access space. Bit Bit Name Initial Value* R/W Description 7 6 5 4 3 2 1 0 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 R/W R/W R/W R/W R/W R/W R/W R/W Area 7 to 0 Bus Width Control Note: * 6.3.
Section 6 Bus Controller (BSC) 6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL) WTCRA and WTCRB select the number of program wait states for each area in the external address space. In addition, CAS latency is set when a synchronous DRAM is connected. • WTCRAH Bit Bit Name Initial Value R/W Description 15 — 0 R Reserved This bit is always read as 0 and cannot be modified.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 9 8 W62 W61 W60 1 1 1 R/W R/W R/W Area 6 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 6 while AST6 bit in ASTCR = 1.
Section 6 Bus Controller (BSC) • WTCRAL Bit Bit Name Initial Value R/W Description 7 — 0 R Reserved This bit is always read as 0 and cannot be modified. 6 5 4 W52 W51 W50 1 1 1 R/W R/W R/W Area 5 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 5 while AST5 bit in ASTCR = 1.
Section 6 Bus Controller (BSC) • WTCRBH Bit Bit Name Initial Value R/W Description 15 — 0 R Reserved This bit is always read as 0 and cannot be modified. 14 13 12 W32 W31 W30 1 1 1 R/W R/W R/W Area 3 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 3 while AST3 bit in ASTCR = 1.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 9 8 W22 W21 W20 1 1 1 R/W R/W R/W Area 2 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 2 while AST2 bit in ASTCR = 1. A CAS latency is set when the synchronous DRAM is connected*. The setting of area 2 is reflected to the setting of areas 2 to 5. A CAS latency can be set regardless of whether or not an ASTCR wait state insertion is enabled.
Section 6 Bus Controller (BSC) • WTCRBL Bit Bit Name Initial Value R/W Description 7 — 0 R Reserved This bit is always read as 0 and cannot be modified. 6 5 4 W12 W11 W10 1 1 1 R/W R/W R/W Area 1 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 1 while AST1 bit in ASTCR = 1.
Section 6 Bus Controller (BSC) 6.3.4 Read Strobe Timing Control Register (RDNCR) RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 RDN7 RDN6 RDN5 RDN4 RDN3 RDN2 RDN1 RDN0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read Strobe Timing Control 7 to 0 These bits set the negation timing of the read strobe in a corresponding area read access. As shown in figure 6.
Section 6 Bus Controller (BSC) 6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL) CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip select signals (CSn) and address signals is to be extended. Extending the assertion period of the CSn and address signals allows flexible interfacing to external I/O devices.
Section 6 Bus Controller (BSC) Bus cycle Th T1 T2 T3 φ Address CS RD Read Data HWR, LWR Write Data Figure 6.3 CS and Address Assertion Period Extension (Example of 3-State Access Space and RDNn = 0) Rev.7.00 Mar.
Section 6 Bus Controller (BSC) 6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) BROMCRH and BROMCRL are used to make burst ROM interface settings. Area 0 and area 1 burst ROM interface settings can be made independently in BROMCRH and BROMCRL, respectively. Bit Bit Name Initial Value R/W Description 7 BSRMn 0 R/W Burst ROM Interface Select Selects the basic bus interface or burst ROM interface.
Section 6 Bus Controller (BSC) 6.3.7 Bus Control Register (BCR) BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. Bit Bit Name Initial Value R/W Description 15 BRLE 0 R/W External Bus Release Enable Enables or disables external bus release.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 ICIS0 1 R/W Idle Cycle Insert 0 When an external read cycle and external write cycle are performed consecutively, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted 9 WDBE 0 R/W Write Data Buffer Enable The write data buffer function can be used for an external write cycle or DMAC single address transfer cycle.
Section 6 Bus Controller (BSC) 6.3.8 DRAM Control Register (DRAMCR) DRAMCR is used to make DRAM/synchronous DRAM interface settings. Note: The synchronous DRAM interface is not supported by the H8S/2378 Group. Bit Bit Name Initial Value R/W Description 15 OEE 0 R/W OE Output Enable The OE signal used when EDO page mode DRAM is connected can be output from the (OE) pin. The OE signal is common to all areas designated as DRAM space.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 12 CAST 0 R/W Column Address Output Cycle Number Select Selects whether the column address output cycle in DRAM access comprises 3 states or 2 states. The setting of this bit applies to all areas designated as DRAM space. 0: Column address output cycle comprises 2 states 1: Column address output cycle comprises 3 states 11 — 0 R/W Reserved This bit can be read from or written to.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 9 8 RMTS2 RMTS1 RMTS0 0 0 0 R/W R/W R/W DRAM/Continuous Synchronous DRAM Space Select These bits designate DRAM/continuous synchronous DRAM space for areas 2 to 5. When continuous DRAM space is set, it is possible to connect large-capacity DRAM exceeding 2 Mbytes per area. In this case, the RAS signal is output from the CS2 pin.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 6 RCDM 0 R/W RAS Down Mode When access to DRAM space is interrupted by an access to normal space, an access to an internal I/O register, etc., this bit selects whether the RAS signal is held low while waiting for the next DRAM access (RAS down mode), or is driven high again (RAS up mode). The setting of this bit is valid only when the BE bit is set to 1.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 4 EDDS 0 R/W EXDMAC Single Address Transfer Option Selects whether full access is always performed or burst access is enabled when EXDMAC single address transfer is performed on the DRAM/synchronous DRAM. When the BE bit is cleared to 0 in DRAMCR, disabling DRAM/synchronous DRAM burst access, EXDMAC single address transfer is performed in full access mode regardless of the setting of this bit.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 2 1 0 MXC2 MXC1 MXC0 0 0 0 R/W R/W R/W Address Multiplex Select These bits select the size of the shift toward the lower half of the row address in row address/column address multiplexing. In burst operation on the DRAM/synchronous DRAM interface, these bits also select the row address bits to be used for comparison.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 2 1 0 MXC2 MXC1 MXC0 0 0 0 R/W R/W R/W 011: 11-bit shift • When 8-bit access space is designated: Row address bits A23 to A11 used for comparison When 16-bit access space is designated: Row address bits A23 to A12 used for comparison Synchronous DRAM interface 100: 8-bit shift • When 8-bit access space is designated: Row address bits A23 to A8 used for comparison • When 16-bit access space is designated: Row address bits
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 2 1 0 MXC2 MXC1 MXC0 0 0 0 R/W R/W R/W 111: 11-bit shift • When 8-bit access space is designated: Row address bits A23 to A11 used for comparison • When 16-bit access space is designated: Row address bits A23 to A12 used for comparison The precharge-sel is A15 to A12 of the column address. Bus cycle Tp Tr Tc1 Tc2 φ Row address Address Column address RAST = 0 RAS RAST = 1 RAS UCAS, LCAS Figure 6.
Section 6 Bus Controller (BSC) 6.3.9 DRAM Access Control Register (DRACCR) DRACCR is used to set the DRAM/synchronous DRAM interface bus specifications. Note: The synchronous DRAM interface is not supported by the H8S/2378 Group. Bit Bit Name Initial Value R/W Description 15 DRMI 0 R/W Idle Cycle Insertion An idle cycle can be inserted after a DRAM/synchronous DRAM access cycle when a continuous normal space access cycle follows a DRAM/synchronous DRAM access cycle.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 ⎯ 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 9 8 RCD1 RCD0 0 0 R/W R/W RAS-CAS Wait Control These bits select a wait cycle to be inserted between the RAS assert cycle and CAS assert cycle. A 1- to 4-state wait cycle can be inserted.
Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Precharge-sel Column address Row address Row address RAS SDWCD 0 CAS WE CKE High DQMU, DQML Data bus Address bus PALL ACTV NOP WRIT Tp Tr Tc1 Tc2 Column address Precharge-sel Row address NOP Column address Row address RAS SDWCD 1 CAS WE CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT Figure 6.
Section 6 Bus Controller (BSC) 6.3.10 Refresh Control Register (REFCR) REFCR specifies DRAM/synchronous DRAM interface refresh control. Note: The synchronous DRAM interface is not supported by the H8S/2378 Group. Bit Bit Name Initial Value R/W Description 15 CMF 0 R/(W)* Compare Match Flag Status flag that indicates a match between the values of RTCNT and RTCOR.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 11 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 10 9 8 RTCK2 RTCK1 RTCK0 0 0 0 R/W R/W R/W Refresh Counter Clock Select These bits select the clock to be used to increment the refresh counter. When the input clock is selected with bits RTCK2 to RTCK0, the refresh counter begins counting up.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 5 4 RLW1 RLW0 0 0 R/W R/W Refresh Cycle Wait Control These bits select the number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle/synchronous DRAM interface autorefresh cycle. This setting applies to all areas designated as DRAM/continuous synchronous DRAM space.
Section 6 Bus Controller (BSC) 6.3.11 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits RTCK2 to RTCK0 in REFCR. When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and RTCNT is cleared to H'00. If the RFSHE bit in REFCR is set to 1 at this time, a refresh cycle is started. If the RFSHE bit is cleared to 0 and the CMIE bit in REFCR is set to 1, a compare match interrupt (CMI) is generated.
Section 6 Bus Controller (BSC) 6.4 Bus Control 6.4.1 Area Division The bus controller divides the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external address space in area units. Chip select signals (CS0 to CS7) can be output for each area. In normal mode, a part of area 0, 64-kbyte address space, is controlled. Figure 6.6 shows an outline of the memory map.
Section 6 Bus Controller (BSC) 6.4.2 Bus Specifications The external address space bus specifications consist of five elements: bus width, number of access states, number of program wait states, read strobe timing, and chip select (CS) assertion period extension states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR.
Section 6 Bus Controller (BSC) Table 6.
Section 6 Bus Controller (BSC) 6.4.3 Memory Interfaces The memory interfaces in this LSI comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; a synchronous DRAM interface that allows direct connection of synchronous DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area.
Section 6 Bus Controller (BSC) If areas 2 to 5 are designated as continuous synchronous DRAM space, large-capacity (e.g. 64Mbit) synchronous DRAM can be connected. In this case, the CS2, CS3, CS4, and CS5 pins are used as the RAS, CAS, WE, and CLK signals for the continuous synchronous DRAM space. The OE pin is used as the CKE signal. Area 6: In externally expanded mode, all of area 6 is external space. When area 6 external space is accessed, the CS6 signal can be output.
Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus Area n external address CSn Figure 6.7 CSn Signal Output Timing (n = 0 to 7) 6.5 Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 6.5.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword.
Section 6 Bus Controller (BSC) Upper data bus D15 Lower data bus D8 D7 D0 Byte size Word size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space) 16-Bit Access Space: Figure 6.9 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses.
Section 6 Bus Controller (BSC) 6.5.2 Valid Strobes Table 6.3 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.
Section 6 Bus Controller (BSC) Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space Rev.7.00 Mar.
Section 6 Bus Controller (BSC) 8-Bit, 3-State Access Space: Figure 6.11 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states can be inserted. Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 D7 to D0 Valid High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.
Section 6 Bus Controller (BSC) for odd addresses, and the lower half (D7 to D0) for even addresses. Wait states cannot be inserted. Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access) Rev.7.00 Mar.
Section 6 Bus Controller (BSC) Bus cycle T2 T1 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write High impedance D15 to D8 D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) Rev.7.00 Mar.
Section 6 Bus Controller (BSC) Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Rev.7.00 Mar.
Section 6 Bus Controller (BSC) 16-Bit, 3-State Access Space: Figures 6.15 to 6.17 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Notes: 1. n = 0 to 7 2.
Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) Rev.7.00 Mar.
Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space (Word Access) Rev.7.00 Mar.
Section 6 Bus Controller (BSC) 6.5.4 Wait Control When accessing external space, this LSI can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 7 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings in WTCRA and WTCRB.
Section 6 Bus Controller (BSC) By program wait T1 T2 Tw By WAIT pin Tw Tw T3 φ WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Notes: 1. Downward arrows indicate the timing of WAIT pin sampling. 2. When RDN = 0 Figure 6.18 Example of Wait State Insertion Timing 6.5.5 Read Strobe (RD) Timing The read strobe (RD) timing can be changed for individual areas by setting bits RDN7 to RDN0 to 1 in RDNCR. Figure 6.
Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus CSn AS RD RDNn = 0 Data bus RD RDNn = 1 Data bus DACK, EDACK Figure 6.19 Example of Read Strobe Timing 6.5.6 Extension of Chip Select (CS) Assertion Period Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, HWR, and LWR.
Section 6 Bus Controller (BSC) Figure 6.20 shows an example of the timing when the CS assertion period is extended in basic bus 3-state access space. Bus cycle Th T1 T2 T3 Tt φ Address bus CSn AS Read (when RDNn = 0) RD Data bus Read data HWR, LWR Write Data bus Write data Figure 6.
Section 6 Bus Controller (BSC) 6.6 DRAM Interface In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst operation is also possible, using fast page mode. 6.6.1 Setting DRAM Space Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR.
Section 6 Bus Controller (BSC) Table 6.
Section 6 Bus Controller (BSC) 6.6.4 Pins Used for DRAM Interface Table 6.6 shows the pins used for DRAM interfacing and their functions. Since the CS2 to CS5 pins are in the input state after a reset, set the corresponding DDR to 1 when RAS2 to RAS5 signals are output. Table 6.
Section 6 Bus Controller (BSC) 6.6.5 Basic Timing Figure 6.21 shows the basic access timing for DRAM space. The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states. Tp Tr Tc1 Tc2 φ Address bus Row address Column address RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2 to 5 Figure 6.
Section 6 Bus Controller (BSC) space to be output from a dedicated OE pin. In this case, the OE signal for DRAM space is output from both the RD pin and the (OE) pin, but in external read cycles for other than DRAM space, the signal is output only from the RD pin. 6.6.6 Column Address Output Cycle Control The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit to 1 in DRAMCR. Use the setting that gives the optimum specification values (CAS pulse width, etc.
Section 6 Bus Controller (BSC) 6.6.7 Row Address Output State Control If the RAST bit is set to 1 in DRAMCR, the RAS signal goes low from the beginning of the Tr state, and the row address hold time and DRAM read access time are changed relative to the fall of the RAS signal. Use the optimum setting according to the DRAM connected and the operating frequency of this LSI. Figure 6.23 shows an example of the timing when the RAS signal goes low from the beginning of the Tr state.
Section 6 Bus Controller (BSC) If a row address hold time or read access time is necessary, making a setting in bits RCD1 and RCD0 in DRACCR allows from one to three Trw states, in which row address output is maintained, to be inserted between the Tr cycle, in which the RAS signal goes low, and the Tc1 cycle, in which the column address is output.
Section 6 Bus Controller (BSC) 6.6.8 Precharge State Control When DRAM is accessed, a RAS precharge time must be secured. With this LSI, one Tp state is always inserted when DRAM space is accessed. From one to four Tp states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the DRAM connected and the operating frequency of this LSI. Figure 6.25 shows the timing when two Tp states are inserted.
Section 6 Bus Controller (BSC) 6.6.9 Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Wait states are inserted to extend the CAS assertion period in a read access to DRAM space, and to extend the write data setup time relative to the falling edge of CAS in a write access.
Section 6 Bus Controller (BSC) By program wait Tp Tr Tc1 Tw By WAIT pin Tw φ WAIT Address bus Row address Column address RASn (CSn) UCAS, LCAS Read WE (HWR) High OE (RD) Data bus UCAS, LCAS Write WE (HWR) OE (RD) High Data bus Note: Downward arrows indicate the timing of WAIT pin sampling. n = 2 to 5 Figure 6.26 Example of Wait State Insertion Timing (2-State Column Address Output) Rev.7.00 Mar.
Section 6 Bus Controller (BSC) Tp Tr By program wait By WAIT pin Tc1 Tw Tw Tc2 Tc3 φ WAIT Address bus Row address Column address RASn (CSn) UCAS, LCAS Read WE (HWR) High OE (RD) Data bus UCAS, LCAS Write WE (HWR) OE (RD) High Data bus Note: Downward arrows indicate the timing of WAIT pin sampling. n = 2 to 5 Figure 6.27 Example of Wait State Insertion Timing (3-State Column Address Output) Rev.7.00 Mar.
Section 6 Bus Controller (BSC) 6.6.10 Byte Access Control When DRAM with a ×16-bit configuration is connected, the 2-CAS access method is used for the control signals needed for byte access. Figure 6.28 shows the control timing for 2-CAS access, and figure 6.29 shows an example of 2-CAS DRAM connection. Tp Tr Tc1 Tc2 φ Address bus Row address Column address RASn (CSn) UCAS LCAS High WE (HWR) OE (RD) High Write data Upper data bus High impedance Lower data bus Note: n = 2 to 5 Figure 6.
Section 6 Bus Controller (BSC) This LSI (Address shift size set to 10 bits) 2-CAS type 16-Mbit DRAM 1-Mbyte × 16-bit configuration 10-bit column address RASn (CSn) RAS UCAS UCAS LCAS LCAS HWR (WE) RD (OE) A10 WE OE A9 A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D15 to D0 Row address input: A9 to A0 Column address input: A9 to A0 D15 to D0 Figure 6.29 Example of 2-CAS DRAM Connection 6.6.
Section 6 Bus Controller (BSC) Tp Tr Tc1 Tc2 Tc1 Tc2 φ Address bus Row address Column address 1 Column address 2 RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2 to 5 Figure 6.30 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0) Rev.7.00 Mar.
Section 6 Bus Controller (BSC) Tp Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3 φ Address bus Row address Column address 1 Column address 2 RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2 to 5 Figure 6.31 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1) The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are the same as for full access. For details see section 6.6.
Section 6 Bus Controller (BSC) ⎯ a refresh operation is initiated in the RAS down state ⎯ self-refreshing is performed ⎯ the chip enters software standby mode ⎯ the external bus is released ⎯ the RCDM bit or BE bit is cleared to 0 If a transition is made to the all-module-clocks-stopped mode in the RAS down state, the clock will stop with RAS low. To enter the all-module-clocks-stopped mode with RAS high, the RCDM bit must be cleared to 0 before executing the SLEEP instruction.
Section 6 Bus Controller (BSC) • RAS Up Mode To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6.33 shows an example of the timing in RAS up mode.
Section 6 Bus Controller (BSC) 6.6.12 Refresh Control This LSI is provided with a DRAM refresh control function. CAS-before-RAS (CBR) refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when any area is designated as DRAM space in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR. CAS-before-RAS (CBR) Refreshing: To select CBR refreshing, set the RFSHE bit to 1 in REFCR.
Section 6 Bus Controller (BSC) φ RTCNT N H'00 RTCOR N Refresh request signal and CMF bit setting signal Figure 6.35 Compare Match Timing TRp TRr TRc1 TRc2 φ CSn (RASn) UCAS, LCAS Figure 6.36 CBR Refresh Timing A setting can be made in bits RCW1 and RCW0 in REFCR to delay RAS signal output by one to three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the RAS signal. The settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations. Figure 6.
Section 6 Bus Controller (BSC) TRp TRrw TRr TRc1 TRc2 φ CSn (RASn) UCAS, LCAS Figure 6.37 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0) Depending on the DRAM used, modification of the WE signal may not be permitted during the refresh period. In this case, the CBRM bit in REFCR should be set to 1. The bus controller will then insert refresh cycles in appropriate breaks between bus cycles. Figure 6.38 shows an example of the timing when the CBRM bit is set to 1.
Section 6 Bus Controller (BSC) Normal space access request φ A23 to A0 CS AS RD HWR (WE) Refresh period RAS CAS Figure 6.38 Example of CBR Refresh Timing (CBRM = 1) Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in REFCR.
Section 6 Bus Controller (BSC) TRp Software standby TRr TRc3 φ CSn (RASn) UCAS, LCAS HWR (WE) High Note: n = 2 to 5 Figure 6.39 Self-Refresh Timing In some DRAMs provided with a self-refresh mode, the RAS signal precharge time immediately after self-refreshing is longer than the normal precharge time. A setting can be made in bits TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self-refreshing from 1 to 7 states longer than the normal precharge time.
Section 6 Bus Controller (BSC) Software standby DRAM space write Trc3 Trp1 Trp2 Tp Tr Tc1 Tc2 φ Address bus RASn (CSn) UCAS, LCAS OE (RD) WR (HWR) Data bus Note: n = 2 to 5 Figure 6.
Section 6 Bus Controller (BSC) When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only, irrespective of the bus master. With the DRAM interface, the DACK or EDACK output goes low from the Tc1 state. Figure 6.41 shows the DACK or EDACK output timing for the DRAM interface when DDS = 1 or EDDS = 1.
Section 6 Bus Controller (BSC) When DDS = 0 or EDDS = 0: When DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access (normal access) is always performed. With the DRAM interface, the DACK or EDACK output goes low from the Tr state. In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used when accessing DRAM space. Figure 6.42 shows the DACK or EDACK output timing for the DRAM interface when DDS = 0 or EDDS = 0.
Section 6 Bus Controller (BSC) 6.7 Synchronous DRAM Interface In the H8S/2378R Group, external address space areas 2 to 5 can be designated as continuous synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Synchronous DRAM of CAS latency 1 to 4 can be connected.
Section 6 Bus Controller (BSC) Commands that are supported by this LSI are NOP, auto-refresh (REF), self-refresh (SELF), all bank precharge (PALL), row address strobe bank-active (ACTV), read (READ), write (WRIT), and mode-register write (MRS). Commands for bank control cannot be used. 6.7.2 Address Multiplexing With continuous synchronous DRAM space, the row address and column address are multiplexed.
Section 6 Bus Controller (BSC) 6.7.3 Data Bus If the ABW2 bit in ABWCR corresponding to an area designated as continuous synchronous DRAM space is set to 1, area 2 to 5 are designated as 8-bit continuous synchronous DRAM space; if the bit is cleared to 0, the areas are designated as 16-bit continuous synchronous DRAM space. In 16-bit continuous synchronous DRAM space, ×16-bit configuration synchronous DRAM can be connected directly.
Section 6 Bus Controller (BSC) Table 6.
Section 6 Bus Controller (BSC) 6.7.5 Synchronous DRAM Clock When the DCTL pin is fixed to 1, synchronous clock (SDRAMφ) is output from the CS5 pin. When the frequency multiplication factor of the PLL circuit of this LSI is set to ×1 or ×2, SDRAMφ is 90° phase shift from φ. Therefore, a stable margin is ensured for the synchronous DRAM that operates at the rising edge of clocks. Figure 6.43 shows the relationship between φ and SDRAMφ.
Section 6 Bus Controller (BSC) Tp Tr Column address Row address Tc1 Tc2 φ SDRAMφ Address bus Precharge-sel Column address Row address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT Figure 6.44 Basic Access Timing of Synchronous DRAM (CAS Latency 1) Rev.7.00 Mar.
Section 6 Bus Controller (BSC) 6.7.7 CAS Latency Control CAS latency is controlled by settings of the W22 to W20 bits of WTCRB. Set the CAS latency count, as shown in table 6.10, by the setting of synchronous DRAM. Depending on the setting, the CAS latency control cycle (Tc1) is inserted. WTCRB can be set regardless of the setting of the AST2 bit of ASTCR. Figure 6.45 shows the CAS latency control timing when synchronous DRAM of CAS latency 3 is connected. The initial value of W22 to W20 is H'7.
Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl1 Tcl2 Tc2 φ SDRAMφ Address bus Column address Row address Precharge-sel Row address Column address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP Figure 6.45 CAS Latency Control Timing (SDWCD = 0, CAS Latency 3) Rev.7.00 Mar.
Section 6 Bus Controller (BSC) 6.7.8 Row Address Output State Control When the command interval specification from the ACTV command to the next READ/WRIT command cannot be satisfied, 1 to 3 states (Trw) that output the NOP command can be inserted between the Tr cycle that outputs the ACTV command and the Tc1 cycle that outputs the column address by setting the RCD1 and RCD0 bits of DRACCR.
Section 6 Bus Controller (BSC) 6.7.9 Precharge State Count When the interval specification from the PALL command to the next ACTV/REF command cannot be satisfied, from one to four Tp states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.47 shows the timing when two Tp states are inserted. Rev.7.00 Mar.
Section 6 Bus Controller (BSC) The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh cycles. Tp1 Tp2 Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Row address Column address Row address Precharge-sel RAS CAS Read WE CKE High DQMU, DQML Data bus PALL NOP ACTV READ NOP RAS CAS Write WE CKE High DQMU, DQML Data bus PALL NOP ACTV NOP WRIT NOP Figure 6.
Section 6 Bus Controller (BSC) 6.7.10 Bus Cycle Control in Write Cycle By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (Tc1) that is inserted by the WTCRB register in the write access of the synchronous DRAM can be disabled. Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to synchronous DRAM read access. Figure 6.48 shows the write access timing when the CAS latency control cycle is disabled.
Section 6 Bus Controller (BSC) 6.7.11 Byte Access Control When synchronous DRAM with a ×16-bit configuration is connected, DQMU and DQML are used for the control signals needed for byte access. Figures 6.49 and 6.50 show the control timing for DQM, and figure 6.51 shows an example of connection of byte control by DQMU and DQML.
Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Row address Precharge-sel Row address Column address RAS CAS WE CKE High DQMU High DQML Upper data bus High impedance Lower data bus PALL ACTV READ NOP Figure 6.50 DQMU and DQML Control Timing (Lower Byte Read Access: CAS Latency 2) Rev.7.00 Mar.
Section 6 Bus Controller (BSC) This LSI (Address shift size set to 8 bits) CS2 (RAS) RAS CS3 (CAS) CAS CS4 (WE) WE UCAS (DQMU) DQMU LCAS (DQML) DQML CS5 (SDRAMφ) CLK A23 A13 (BS1) A21 A12 (BS0) A12 A11 A11 A10 A10 A9 A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D15 to D0 DCTL 64-Mbit synchronous DRAM 1 Mword × 16 bits × 4-bank configuration 8-bit column address OE (CKE) I/O PORT Row address input: A11 to A0 Column address input: A7 to A0 Bank select ad
Section 6 Bus Controller (BSC) 6.7.12 Burst Operation With synchronous DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, burst access is also provided which can be used when making consecutive accesses to the same row address. This access enables fast access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit to 1 in DRAMCR.
Section 6 Bus Controller (BSC) Tp Tr Column address 1 Row address Tc1 Tcl Tc2 Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Column address 2 Row address Precharge-sel RAS CAS Read WE CKE High DQMU, DQML Data bus PALL ACTV READ NOP READ NOP RAS CAS Write WE CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP Figure 6.52 Operation Timing of Burst Access (BE = 1, SDWCD = 0, CAS Latency 2) Rev.7.00 Mar.
Section 6 Bus Controller (BSC) RAS Down Mode: Even when burst operation is selected, it may happen that access to continuous synchronous DRAM space is not continuous, but is interrupted by access to another space. In this case, if the row address active state is held during the access to the other space, the read or write command can be issued without ACTV command generation similarly to DRAM RAS down mode. To select RAS down mode, set the BE bit to 1 in DRAMCR regardless of the RCDM bit settings.
Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl External space read Tc2 T1 T2 Continuous synchronous DRAM space read Tc1 Tcl Tc2 φ Address bus Column Row address address Precharge-sel Row address Column address External address Column address 2 External address RAS CAS WE CKE High DQMU, DQML Data bus PALL ACTV READ NOP READ NOP Figure 6.53 Example of Operation Timing in RAS Down Mode (BE = 1, CAS Latency 2) 6.7.
Section 6 Bus Controller (BSC) Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval specification for the synchronous DRAM used. When bits RTCK2 to RTCK0 are set, RTCNT starts counting up. RTCNT and RTCOR settings should therefore be completed before setting bits RTCK2 to RTCK0. Auto refresh timing is shown in figure 6.54. Since the refresh counter operation is the same as the operation in the DRAM interface, see section 6.6.12, Refresh Control.
Section 6 Bus Controller (BSC) TPC1 and TPC0 of DRACCR is also valid in refresh cycles, the command interval can be extended by the RCW1 and RCW0 bits after the precharge cycles. TRp1 TRrw TRp2 TRr TRc1 TRc2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE CKE High PALL NOP REF NOP Figure 6.
Section 6 Bus Controller (BSC) TRp TRr TRr1 TRcw TRc2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE CKE High PALL REF NOP Figure 6.56 Auto Refresh Timing (TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1) Self-Refreshing: A self-refresh mode (battery backup mode) is provided for synchronous DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the synchronous DRAM. To select self-refreshing, set the RFSHE bit to 1 in REFCR.
Section 6 Bus Controller (BSC) TRp TRr PALL SELF Software standby TRc2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE CKE NOP Figure 6.57 Self-Refresh Timing (TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0) In some synchronous DRAMs provided with a self-refresh mode, the interval between clearing self-refreshing and the next command is specified.
Section 6 Bus Controller (BSC) Continuous synchronous DRAM space write Software standby TRc2 TRp1 TRp2 Tp Tr Column address Row address Tc1 Tcl Tc2 φ SDRAMφ Address bus Precharge-sel Column address Row address RAS CAS WE CKE DQMU, DQML Data bus NOP PALL ACTV NOP NOP NOP Figure 6.
Section 6 Bus Controller (BSC) 6.7.14 Mode Register Setting of Synchronous DRAM To use synchronous DRAM, mode must be set after power-on. To set mode, set the RMTS2 to RMTS0 bits in DRAMCR to H'5 and enable the synchronous DRAM mode register setting. After that, access the continuous synchronous DRAM space in bytes.
Section 6 Bus Controller (BSC) 6.7.15 DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM Interface When burst mode is selected on the synchronous DRAM interface, the DACK and EDACK output timing can be selected with the DDS and EDDS bits in DRAMCR. When continuous synchronous DRAM space is accessed in DMAC/EXDMAC single address mode at the same time, these bits select whether or not burst access is to be performed.
Section 6 Bus Controller (BSC) Tp Tr Column address Row address Tc1 Tcl Tc2 φ SDRAMφ Address bus Precharge-sel Column address Row address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP DACK or EDACK Figure 6.60 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1 Rev.7.00 Mar.
Section 6 Bus Controller (BSC) When DDS = 0 or EDDS = 0: When continuous synchronous DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access (normal access) is always performed. With the synchronous DRAM interface, the DACK or EDACK output goes low from the Tr state. In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used when accessing continuous synchronous DRAM space. Figure 6.
Section 6 Bus Controller (BSC) Tr Tp Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Row address Precharge-sel Row address Column address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP DACK or RDACK Figure 6.61 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0 Rev.7.00 Mar.
Section 6 Bus Controller (BSC) (2) Read Data Extension If the CKSPE bit is set to 1 in DRACCR when the continuous synchronous DRAM space is readaccessed in DMAC/EXDMAC single address mode, the establishment time for the read data can be extended by clock suspend mode. The number of states for insertion of the read data extension cycle (Tsp) is set in bits RDXC1 and RDXC0 in DRACCR. Be sure to set the OEE bit to 1 in DRAMCR when the read data will be extended.
Section 6 Bus Controller (BSC) 6.8 Burst ROM Interface In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst ROM interfacing performed. The burst ROM space enables ROM with burst access capability to be accessed at high speed. Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in BROMCR. Continuous burst accesses of 4, 8, 16, or 32 words can be performed, according to the setting of the BSWD11 and BSWD10 bits in BROMCR.
Section 6 Bus Controller (BSC) Full access T1 T2 Burst access T3 T1 T2 T1 T2 φ Upper address bus Lower address bus CSn AS RD Data bus Note: n = 1 and 0 Figure 6.63 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle) Rev.7.00 Mar.
Section 6 Bus Controller (BSC) Full access T1 T2 Burst access T1 T1 φ Upper address bus Lower address bus CSn AS RD Data bus Note: n = 1 and 0 Figure 6.64 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle) 6.8.2 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) on the burst ROM interface. See section 6.5.4, Wait Control.
Section 6 Bus Controller (BSC) 6.9 Idle Cycle 6.9.1 Operation When this LSI accesses external address space, it can insert an idle cycle (Ti) between bus cycles in the following three cases: (1) when read accesses in different areas occur consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs immediately after a write cycle. Insertion of a 1-state or 2-state idle cycle can be selected with the IDLC bit in BCR.
Section 6 Bus Controller (BSC) Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.66 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle.
Section 6 Bus Controller (BSC) Read after Write: If an external read occurs after an external write while the ICIS2 bit is set to 1 in BCR, an idle cycle is inserted at the start of the read cycle. Figure 6.67 shows an example of the operation in this case. In this example, bus cycle A is a CPU write cycle and bus cycle B is a read cycle from an external device. In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the CPU write data and read data from an external device.
Section 6 Bus Controller (BSC) Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.68. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals.
Section 6 Bus Controller (BSC) Idle Cycle in Case of DRAM Space Access after Normal Space Access: In a DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas, for example, if the second read is a full access to DRAM space, only a Tp cycle is inserted, and a Ti cycle is not. The timing in this case is shown in figure 6.69.
Section 6 Bus Controller (BSC) DRAM space read Tp Tr Tc1 External read Tc2 T1 T2 T3 DRAM space read Ti Tc1 Tc2 φ Address bus RD RAS UCAS, LCAS Data bus Idle cycle Figure 6.70 Example of Idle Cycle Operation in RAS Down Mode (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) DRAM space read Tp Tr Tc1 External read Tc2 T1 T2 T3 DRAM space write Ti Tc1 Tc2 φ Address bus RD HWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.
Section 6 Bus Controller (BSC) Idle Cycle in Case of Continuous Synchronous DRAM Space Access after Normal Space Access: In a continuous synchronous DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas, for example, if the second read is a full access to continuous synchronous DRAM space, only Tp cycle is inserted, and Ti cycle is not. The timing in this case is shown in figure 6.
Section 6 Bus Controller (BSC) 6.73 and 6.74. In write access, DQMU and DQML are not in accordance with the settings of the IDLC bit. The timing in this case is illustrated in figure 6.75.
Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl Continuous synchronous DRAM space read External space read Tc2 T1 T2 T3 Ti Ti Tc1 TCl Tc2 φ Address bus Row Column address address Precharge-sel Row address Column address 1 External address Column address 2 External address RAS CAS WE CKE High DQMU, DQML RD HWR, LWR High Data bus PALL ACTV READ NOP READ NOP Idle cycle Figure 6.
Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl External space read Tc2 T1 T2 T3 Continuous synchronous DRAM space write Ti Tc1 TCl Tc2 φ Address bus Row Column address address Precharge-sel Row address Column address 1 External address Column address 2 External address RAS CAS WE CKE High DQMU, DQML RD HWR, LWR High Data bus PALL ACTV READ NOP WRIT Idle cycle Figure 6.
Section 6 Bus Controller (BSC) Idle Cycle in Case of Normal Space Access after DRAM Space Access: • Normal space access after DRAM space read access While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access is disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI bit to 1. The conditions and number of states of the idle cycle to be inserted are in accordance with the settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.
Section 6 Bus Controller (BSC) DRAM space read Tp Tr Tc1 External address space write DRAM space read Tc2 Ti T1 T2 T3 Tc1 Tc2 φ Address bus RD HWR, LWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.77 Example of Idle Cycle Operation after DRAM Access (Write after Read) (IDLC = 0, RAST = 0, CAST = 0) Rev.7.00 Mar.
Section 6 Bus Controller (BSC) • Normal space access after DRAM space write access While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM space write access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to be inserted is in accordance with the setting of the IDLC bit. It does not depend on the DRMI bit in DRACCR. Figure 6.78 shows an example of idle cycle operation when the ICIS2 bit is set to 1.
Section 6 Bus Controller (BSC) not inserted after continuous synchronous DRAM space read access even if bits ICIS1 and ICIS0 are set to 1.
Section 6 Bus Controller (BSC) • Normal space access after a continuous synchronous DRAM space write access If a normal space read cycle occurs after a continuous synchronous DRAM space write access while the ICIS2 bit is set to 1 in BCR, idle cycle is inserted at the start of the read cycle. The number of states of the idle cycle to be inserted is in accordance with the setting of bit IDLC. It is not in accordance with the DRMI bit in DRACCR. Figure 6.
Section 6 Bus Controller (BSC) Table 6.
Section 6 Bus Controller (BSC) Previous Access Next Access Normal space write Normal space read DRAM*/continuous synchronous DRAM space read DRAM/continuous Normal space read synchronous DRAM* space write DRAM*/continuous synchronous DRAM space read Note: * ICIS2 ICIS1 ICIS0 DRMI IDLC Idle cycle 0 ⎯ ⎯ ⎯ ⎯ Disabled 1 ⎯ ⎯ ⎯ 0 1 state inserted 1 2 states inserted 0 ⎯ ⎯ ⎯ ⎯ Disabled 1 ⎯ ⎯ ⎯ 0 1 state inserted 1 2 states inserted 0 ⎯ ⎯ ⎯ ⎯ Disabled 1 ⎯ ⎯ ⎯ 0 1
Section 6 Bus Controller (BSC) DRAM space read φ Tp Tr Tc1 DRAM space write Tc2 Ti Tc1 Tc2 Address bus RASn (CSn) UCAS, LCAS WE (HWR) OE (RD) Data bus Note: n = 2 to 5 Idle cycle Figure 6.81 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to DRAM Space in RAS Down Mode Rev.7.00 Mar.
Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl Continuous synchronous DRAM space write Tc2 Ti Tc1 Tc2 φ Address bus Column Row address address Column address External address Precharge-sel RAS CAS WE CKE High DQMU, DQML Data bus PALL ACTV READ NOP WRIT Idle cycle Figure 6.82 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to Continuous Synchronous DRAM Space in RAS Down Mode (SDWCD = 1, CAS Latency 2) Rev.
Section 6 Bus Controller (BSC) 6.9.2 Pin States in Idle Cycle Table 6.12 shows the pin states in an idle cycle. Table 6.12 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of following bus cycle D15 to D0 CSn (n = 7 to 0) High impedance 1 2 High* * UCAS, LCAS High* AS High RD High 2 (OE) High HWR, LWR High DACKn (n = 1, 0) High EDACKn (n = 3, 2) High Notes: 1. Remains low in DRAM space RAS down mode. 2. Remains low in a DRAM space refresh cycle. 6.
Section 6 Bus Controller (BSC) On-chip memory read Internal I/O register read External write cycle T1 T2 TW TW T3 φ Internal address bus Internal memory Internal I/O register address Internal read signal A23 to A0 External address CSn External space write HWR, LWR D15 to D0 Figure 6.83 Example of Timing when Write Data Buffer Function Is Used 6.11 Bus Release This LSI can release the external bus in response to a bus request from an external device.
Section 6 Bus Controller (BSC) 6.11.1 Operation In externally expanded mode, the bus can be released to an external device by setting the BRLE bit to 1 in BCR. Driving the BREQ pin low issues an external bus request to this LSI. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus released state.
Section 6 Bus Controller (BSC) 6.11.2 Pin States in External Bus Released State Table 6.13 shows pin states in the external bus released state. Table 6.13 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance CSn (n = 7 to 0) High impedance UCAS, LCAS High impedance AS High impedance RD High impedance (OE) High impedance HWR, LWR High impedance DACKn (n = 1, 0) High EDACKn (n = 3 to 0) High Rev.7.00 Mar.
Section 6 Bus Controller (BSC) 6.11.3 Transition Timing Figure 6.84 shows the timing for transition to the bus released state. External space access cycle CPU cycle External bus released state T1 T2 φ High impedance Address bus High impedance Data bus High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK BREQO [1] [2] [3] [4] [5] [6] [7] [8] [1] Low level of BREQ signal is sampled at rise of φ.
Section 6 Bus Controller (BSC) External space read T1 CPU cycle External bus released state T2 φ SDRAMφ High impedance Address bus High impedance Data bus Row address Precharge-sel High impedance High impedance RAS High impedance CAS High impedance WE High impedance CKE High impedance DQMU, DQML BREQ BACK BREQO NOP PALL [1] [2] NOP [3] NOP [4] [5] [8] [6] [7] [9] [1] Low level of BREQ signal is sampled at rise of φ. [2] PALL command is issued.
Section 6 Bus Controller (BSC) 6.12 Bus Arbitration This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration). There are four bus masters⎯the CPU, DTC, DMAC, and EXDMAC*⎯that perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal.
Section 6 Bus Controller (BSC) 6.12.2 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific timings at which each bus master can relinquish the bus.
Section 6 Bus Controller (BSC) EXDMAC: The EXDMAC sends the bus arbiter a request for the bus when an activation request is generated. As the EXDMAC is used exclusively for transfers to and from the external bus, if the bus is transferred to the EXDMAC, internal accesses by other internal bus masters are still executed in parallel. In normal transfer mode or cycle steal transfer mode, the EXDMAC releases the bus after a single transfer.
Section 6 Bus Controller (BSC) 6.14 Usage Notes 6.14.
Section 6 Bus Controller (BSC) 6.14.4 BREQO Output Timing When the BREQOE bit is set to 1 and the BREQO signal is output, BREQO may go low before the BACK signal. This will occur if the next external access request or CBR refresh request occurs while internal bus arbitration is in progress after the chip samples a low level of BREQ. 6.14.5 Notes on Usage of the Synchronous DRAM Setting of Synchronous DRAM Interface: The DCTL pin must be fixed to 1 to enable the synchronous DRAM interface.
Section 7 DMA Controller (DMAC) Section 7 DMA Controller (DMAC) This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels. 7.
Section 7 DMA Controller (DMAC) A block diagram of the DMAC is shown in figure 7.1. Internal address bus Address buffer DMAWER DMACR0A DMACR0B DMACR1A DMACR1B DMABCR Channel 1 DMATCR MAR_0AH ETCR_0A MAR_0BH IOAR_0B MAR_1AH MAR_1AL IOAR_1A ETCR_1A MAR_1BH Internal data bus : DMA write enable register : DMA terminal control register : DMA band control register (for all channels) : DMA control register : Memory address register : I/O address register : Execute transfer count register Figure 7.
Section 7 DMA Controller (DMAC) 7.2 Input/Output Pins Table 7.1 shows the pin configuration of the interrupt controller. Table 7.
Section 7 DMA Controller (DMAC) • DMA control register_1A (DMACR_1A) • DMA control register_1B (DMACR_1B) • DMA band control register H (DMABCRH) • DMA band control register L (DMABCRL) • DMA write enable register (DMAWER) • DMA terminal control register (DMATCR) The functions of MAR, IOAR, ETCR, DMACR, and DMABCR differ according to the transfer mode (short address mode or full address mode). The transfer mode can be selected by means of the FAE1 and FAE0 bits in DMABCRH.
Section 7 DMA Controller (DMAC) 7.3.1 Memory Address Registers (MARA and MARB) MAR is a 32-bit readable/writable register that specifies the source address (transfer source address) or destination address (transfer destination address). MAR consists of two 16-bit registers MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and cannot be modified.
Section 7 DMA Controller (DMAC) 7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The DMA has four ETCR registers: ETCR_0A in channel 0 (channel 0A), ETCR_0B in channel 0 (channel 0B), ETCR_1A in channel 1 (channel 1A), and ETCR_1B in channel 1 (channel 1B). ETCR is not initialized by a reset or in standby mode.
Section 7 DMA Controller (DMAC) 7.3.4 DMA Control Registers (DMACRA and DMACRB) DMACR controls the operation of each DMAC channel. The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1 (channel 1B). In short address mode, channels A and B operate independently, and in full address mode, channels A and B operate together.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 5 RPE 0 R/W Repeat Enable Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W Data Transfer Factor 3 to 0 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and channel B.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W • 2 DTF2 0 R/W 0000: Setting prohibited 1 DTF1 0 R/W 0 DTF0 0 R/W 0001: Activated by A/D converter conversion end interrupt Channel B 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled) 0011: Activated by DREQ pin low-level input 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 re
Section 7 DMA Controller (DMAC) Full Address Mode: • DMACR_0A and DMACR_1A Bit Bit Name Initial Value R/W 15 DTSZ 0 R/W Description Data Transfer Size Selects the size of data to be transferred at one time.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 10 to 8 ⎯ All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. Legend: x: Don’t care • DMACR_0B and DMACR_1B Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W Data Transfer Factor 3 to 0 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W These bits select the data transfer factor (activation source). The factors that can be specified differ between normal mode and block transfer mode.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W • 2 DTF2 0 R/W 0000: Setting prohibited 1 DTF1 0 R/W 0 DTF0 0 R/W 0001: Activated by A/D converter conversion end interrupt Block Transfer Mode 0010: Activated by DREQ pin falling edge input 0011: Activated by DREQ pin low-level input 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 reception complete interrupt 0110: Activated by SCI channel 1 tran
Section 7 DMA Controller (DMAC) 7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL) DMABCR controls the operation of each DMAC channel. The bit functions in the DMACR registers differ according to the transfer mode. Short Address Mode: • DMABCRH Bit Bit Name Initial Value R/W Description 15 FAE1 0 R/W Full Address Enable 1 Specifies whether channel 1 is to be used in short address mode or full address mode. In short address mode, channels 1A and 1B can be used as independent channels.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 12 SAE0 0 R/W Single Address Enable 0 Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode.
Section 7 DMA Controller (DMAC) • DMABCRL Bit Bit Name Initial Value R/W Description 7 DTE1B 0 R/W Data Transfer Enable 1B 6 DTE1A 0 R/W Data Transfer Enable 1A 5 DTE0B 0 R/W Data Transfer Enable 0B 4 DTE0A 0 R/W Data Transfer Enable 0A If the DTE bit is cleared to 0 when DTIE = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTIE1B 0 R/W Data Transfer End Interrupt Enable 1B 2 DTIE1A 0 R/W Data Transfer End Interrupt Enable 1A 1 DTIE0B 0 R/W Data Transfer End Interrupt Enable 0B 0 DTIE0A 0 R/W Data Transfer End Interrupt Enable 0A These bits enable or disable an interrupt to the CPU or DTC when transfer ends.
Section 7 DMA Controller (DMAC) Bit Bit Name 13, 12 — Initial Value R/W Description All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. 11 DTA1 0 R/W Data Transfer Acknowledge 1 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 1.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 9 DTA0 0 R/W Data Transfer Acknowledge 0 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 0. It the DTA0 bit is set to 1 when DTE0 = 1, the internal interrupt source is cleared automatically by DMA transfer. When DTE0 = 1 and DTA0 = 1, the internal interrupt source does not issue an interrupt request to the CPU or DTC.
Section 7 DMA Controller (DMAC) • DMABCRL Bit Bit Name Initial Value R/W Description 7 DTME1 0 R/W Data Transfer Master Enable 1 Together with the DTE1 bit, this bit controls enabling or disabling of data transfer on channel 1. When both the DTME1 bit and DTE1 bit are set to 1, transfer is enabled for channel 1. If channel 1 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME1 bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 6 DTE1 0 R/W Data Transfer Enable 1 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 1. When DTE1 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 5 DTME0 0 R/W Data Transfer Master Enable 0 Together with the DTE0 bit, this bit controls enabling or disabling of data transfer on channel 0. When both the DTME0 bit and DTE0 bit are set to 1, transfer is enabled for channel 0. If channel 0 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME0 bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 4 DTE0 0 R/W Data Transfer Enable 0 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 0. When DTE0 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 2 DTIE1A 0 R/W Data Transfer End Interrupt Enable 1A Enables or disables an interrupt to the CPU or DTC when transfer ends. If the DTE1 bit is cleared to 1 when DTIE1A = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
Section 7 DMA Controller (DMAC) 7.3.6 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for the specific channel, to prevent inadvertent rewriting of registers other than those for the channel concerned.
Section 7 DMA Controller (DMAC) chain transfer. When re-setting the control register area, perform masking by setting bits in DMAWER to prevent modification of the contents of other channels. First transfer area MAR_0A IOAR_0A ETCR_0A MAR_0B IOAR_0B ETCR_0B MAR_1A DTC IOAR_1A ETCR_1A MAR_1B IOAR_1B ETCR_1B Second transfer area using chain transfer DMAWER DMATCR DMACR_0A DMACR_0B DMACR_1A DMACR_1B DMABCR Figure 7.
Section 7 DMA Controller (DMAC) 7.3.7 DMA Terminal Control Register (DMATCR) DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. The TEND pin is available only for channel B in short address mode. Except for the block transfer mode, a transfer end signal asserts in the transfer cycle in which the transfer counter contents reaches 0 regardless of the activation source.
Section 7 DMA Controller (DMAC) 7.4 Activation Sources DMAC activation sources consist of internal interrupt requests, external requests, and autorequests. The DMAC activation sources that can be specified depend on the transfer mode and channel, as shown in table 7.3. Table 7.
Section 7 DMA Controller (DMAC) 7.4.1 Activation by Internal Interrupt Request An interrupt request selected as a DMAC activation source can also simultaneously generate an interrupt request for the CPU or DTC. For details, see section 5, Interrupt Controller. With activation by an internal interrupt request, the DMAC accepts the interrupt request independently of the interrupt controller. Consequently, interrupt controller priority settings are irrelevant.
Section 7 DMA Controller (DMAC) 7.4.2 Activation by External Request If an external request (DREQ pin) is specified as a DMAC activation source, the relevant port should be set to input mode in advance*. Level sensing or edge sensing can be used for external requests. External request operation in normal mode of short address mode or full address mode is described below. When edge sensing is selected, a byte or word is transferred each time a high-to-low transition is detected on the DREQ pin.
Section 7 DMA Controller (DMAC) Table 7.4 DMAC Transfer Modes Transfer Mode Short address mode Transfer Source Dual address mode • TPU channel 0 to 5 compare match/input • 1-byte or 1-word transfer for a single transfer request capture A interrupt • SCI transmission • Specify source and complete interrupt destination addresses to transfer data in two bus cycles.
Section 7 DMA Controller (DMAC) Transfer Mode Full address mode Normal mode Transfer Source Remarks • Auto-request • Max.
Section 7 DMA Controller (DMAC) 7.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.5 summarizes register functions in sequential mode. Table 7.
Section 7 DMA Controller (DMAC) Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N – 1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a data transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer ends.
Section 7 DMA Controller (DMAC) [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Sequential mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] [4] Set each bit in DMACR.
Section 7 DMA Controller (DMAC) Table 7.
Section 7 DMA Controller (DMAC) [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Idle mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] [4] Set each bit in DMACR.
Section 7 DMA Controller (DMAC) IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7 summarizes register functions in repeat mode. Table 7.
Section 7 DMA Controller (DMAC) In repeat mode, operation continues until the DTE bit in DMABCRL is cleared. To end the transfer operation, therefore, the DTE bit should be cleared to 0. A transfer end interrupt request is not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the DTE bit was cleared. Figure 7.7 illustrates operation in repeat mode.
Section 7 DMA Controller (DMAC) [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Repeat mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in both ETCRH and ETCRL.
Section 7 DMA Controller (DMAC) 7.5.5 Single Address Mode Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCRH to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.8 summarizes register functions in single address mode. Table 7.
Section 7 DMA Controller (DMAC) Address T DACK Transfer 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N – 1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.9 Operation in Single Address Mode (When Sequential Mode Is Specified) Figure 7.10 shows an example of the setting procedure for single address mode (when sequential mode is specified). Rev.7.00 Mar.
Section 7 DMA Controller (DMAC) Single address mode setting Set DMABCRH Set transfer source and transfer destination addresses [1] [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Set the SAE bit to 1 to select single address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [2] Set the transfer source address/transfer destination address in MAR.
Section 7 DMA Controller (DMAC) 7.5.6 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCRH to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after data transfer of a byte or word in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 7.
Section 7 DMA Controller (DMAC) Transfer Address TA Address BB Address BA Legend: Address Address Address Address Where : TA TB BA BB LA LB N Address TB = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1)) = Value set in MARA = Value set in MARB = Value set in ETCRA Figure 7.11 Operation in Normal Mode Transfer requests (activation sources) are external requests and auto-requests.
Section 7 DMA Controller (DMAC) Figure 7.12 shows an example of the setting procedure for normal mode. [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Normal mode setting Set DMABCRH [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the number of transfers in ETCRA.
Section 7 DMA Controller (DMAC) 7.5.7 Block Transfer Mode In block transfer mode, data transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCRH and the BLKE bit in DMACRA to 1. In block transfer mode, a data transfer of the specified block size is carried out in response to a single transfer request, and this is executed for the number of times specified in ETCRB.
Section 7 DMA Controller (DMAC) Address TB Address TA 1st block 2nd block Block area Transfer Consecutive transfer of M bytes or words is performed in response to one request Address BB Nth block Address BA Legend: Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (M·N – 1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7.
Section 7 DMA Controller (DMAC) Address TA Address TB Block area Transfer 1st block Consecutive transfer of M bytes or words is performed in response to one request Address BA 2nd block Nth block Address BB Legend: Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (M·N – 1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7.
Section 7 DMA Controller (DMAC) ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this point, an interrupt request is sent to the CPU or DTC. Figure 7.15 shows the operation flow in block transfer mode.
Section 7 DMA Controller (DMAC) Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. Figure 7.16 shows an example of the setting procedure for block transfer mode. [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit.
Section 7 DMA Controller (DMAC) 7.5.8 Basic Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, wordsize transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations.
Section 7 DMA Controller (DMAC) 7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles Short Address Mode: Figure 7.18 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.
Section 7 DMA Controller (DMAC) Full Address Mode (Cycle Steal Mode): Figure 7.19 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.
Section 7 DMA Controller (DMAC) Full Address Mode (Burst Mode): Figure 7.20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (burst mode) is performed from external 16bit, 2-state access space to external 16-bit, 2-state access space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Last transfer cycle Bus release Bus release Burst transfer Figure 7.
Section 7 DMA Controller (DMAC) Full Address Mode (Block Transfer Mode): Figure 7.21 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
Section 7 DMA Controller (DMAC) DMA read Bus release DMA write Bus release DMA read DMA write Bus release Transfer source Transfer destination φ DREQ Address bus DMA control Channel Transfer source Transfer destination Idle Read Write Idle Read Request clear period Request [1] [2] Idle Request clear period Request Minimum of 2 cycles Write Minimum of 2 cycles [3] [4] [5] Acceptance resumes [6] [7] Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level
Section 7 DMA Controller (DMAC) 1 block transfer 1 block transfer DMA read Bus release DMA write DMA Bus dead release DMA read DMA write DMA dead Bus release φ DREQ Address bus DMA control Channel Transfer source Read Idle Request Transfer destination Write Idle Dead Request clear period [2] Read Write Transfer destination Dead Idle Request clear period Request Minimum of 2 cycles [1] Transfer source Minimum of 2 cycles [3] [4] [5] [6] Acceptance resumes [7] Acceptance re
Section 7 DMA Controller (DMAC) DREQ Pin Low Level Activation Timing (Normal Mode): Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.24 shows an example of normal mode transfer activated by the DREQ pin low level.
Section 7 DMA Controller (DMAC) 1 block transfer DMA read Bus release 1 block transfer DMA write DMA Bus dead release DMA read DMA write DMA dead Bus release φ DREQ Address bus DMA control Channel Transfer source Read Idle Dead Write Request clear period Request Idle [2] Read Write Transfer destination Dead Idle Request clear period Request Minimum of 2 cycles [1] Transfer source Transfer destination Minimum of 2 cycles [3] [4] [5] [6] Acceptance resumes [7] Acceptance re
Section 7 DMA Controller (DMAC) 7.5.10 DMA Transfer (Single Address Mode) Bus Cycles Single Address Mode (Read): Figure 7.26 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read DMA read DMA read DMA DMA read dead φ Address bus RD DACK TEND Bus release Bus release Bus release Bus Last transfer cycle release Bus release Figure 7.
Section 7 DMA Controller (DMAC) DMA read DMA read DMA read DMA dead φ Address bus RD DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.27 Example of Single Address Mode (Word Read) Transfer A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
Section 7 DMA Controller (DMAC) Single Address Mode (Write): Figure 7.28 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write DMA DMA write dead φ Address bus HWR LWR DACK TEND Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7.28 Example of Single Address Mode Transfer (Byte Write) Figure 7.
Section 7 DMA Controller (DMAC) DMA write DMA write DMA write DMA dead φ Address bus HWR LWR DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.29 Example of Single Address Mode Transfer (Word Write) A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
Section 7 DMA Controller (DMAC) Bus release DMA single Bus release DMA single Bus release φ DREQ Transfer source/ destination Address bus Transfer source/ destination DACK DMA control Channel Idle Single Request Idle Request clear period Single [1] [2] Request clear period Request Minimum of 2 cycles Idle Minimum of 2 cycles [3] [4] [5] Acceptance resumes [6] [7] Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, a
Section 7 DMA Controller (DMAC) DREQ Pin Low Level Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.31 shows an example of single address mode transfer activated by the DREQ pin low level.
Section 7 DMA Controller (DMAC) When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. 7.5.
Section 7 DMA Controller (DMAC) Figure 7.33 shows an example of single address transfer using the write data buffer function. In this example, the CPU program area is in on-chip memory. DMA read DMA single CPU read DMA single CPU read φ Internal address Internal read signal External address RD DACK Figure 7.
Section 7 DMA Controller (DMAC) If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released, the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 7.11. During burst transfer, or when one block is being transferred in block transfer, the channel will not be changed until the end of the transfer. Figure 7.
Section 7 DMA Controller (DMAC) 7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles, and EXDMAC When the DMAC accesses external space, contention with a refresh cycle, EXDMAC cycle, or external bus release cycle may arise. In this case, the bus controller will suspend the transfer and insert a refresh cycle, EXDMAC cycle, or external bus release cycle, in accordance with the external bus priority order, even if the DMAC is executing a burst transfer or block transfer.
Section 7 DMA Controller (DMAC) 7.5.14 DMAC and NMI Interrupts When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested.
Section 7 DMA Controller (DMAC) 7.5.15 Forced Termination of DMAC Operation If the DTE bit in DMABCRL is cleared to 0 for the channel currently operating, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit in DMABCRL. Figure 7.36 shows the procedure for forcibly terminating DMAC operation by software.
Section 7 DMA Controller (DMAC) 7.5.16 Clearing Full Address Mode Figure 7.37 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. [1] Clear both the DTE bit and DTME bit in DMABCRL to 0, or wait until the transfer ends and the DTE bit is cleared to 0, then clear the DTME bit to 0.
Section 7 DMA Controller (DMAC) 7.6 Interrupt Sources The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.12 shows the interrupt sources and their priority order. Table 7.
Section 7 DMA Controller (DMAC) 7.7 Usage Notes 7.7.1 DMAC Register Access during Operation Except for forced termination of the DMAC, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below.
Section 7 DMA Controller (DMAC) • If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 7.40. DMA transfer cycle CPU longword read MAR upper word read MAR lower word read DMA read DMA write φ DMA internal address DMA control DMA register operation Idle [1] Transfe source Transfer destination Read Write Idle [2] Note: The lower word of MAR is the updated value after the operation in [1]. Figure 7.
Section 7 DMA Controller (DMAC) 7.7.3 Write Data Buffer Function When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel.
Section 7 DMA Controller (DMAC) However, if the last transfer cycle and a CBR refresh occur simultaneously, note that although the CBR refresh and the last transfer cycle may be executed consecutively, TEND may also go low in this case for the refresh cycle. DMA read DMA write φ Internal address Internal read signal Internal write signal External address HWR, LWR TEND Not output External write by CPU, etc. Figure 7.41 Example in which Low Level Is Not Output at TEND Pin 7.7.
Section 7 DMA Controller (DMAC) 7.7.6 Activation Source Acceptance At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that occurs before write to DMABCRL to enable transfer.
Section 8 EXDMA Controller (EXDMAC) Section 8 EXDMA Controller (EXDMAC) This LSI has a built-in dual-channel external bus transfer DMA controller (EXDMAC). The EXDMAC can carry out high-speed data transfer, in place of the CPU, to and from external devices and external memory with a DACK (DMA transfer notification) facility. 8.
Section 8 EXDMA Controller (EXDMAC) Figure 8.1 shows a block diagram of the EXDMAC. Bus controller Data buffer Control logic EDRAK Processor ETEND EDACK Interrupt request signals to CPU for individual channels Address buffer EDSAR EDDAR EDMDR EDACR EDTCR Internal data bus Legend: EDSAR: EDDAR: EDTCR: EDMDR: EDACR: EXDMA source address register EXDMA destination address register EXDMA transfer count register EXDMA mode control register EXDMA address control register Figure 8.
Section 8 EXDMA Controller (EXDMAC) 8.2 Input/Output Pins Table 8.1 shows the pin configuration of the EXDMAC. Table 8.
Section 8 EXDMA Controller (EXDMAC) 8.3 Register Descriptions The EXDMAC has the following registers.
Section 8 EXDMA Controller (EXDMAC) EDDAR can be read at all times by the CPU. When reading EDDAR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write to EDDAR for a channel on which EXDMA transfer is in progress. The initial values of EDDAR are undefined. 8.3.3 EXDMA Transfer Count Register (EDTCR) EDTCR specifies the number of transfers. The function differs according to the transfer mode.
Section 8 EXDMA Controller (EXDMAC) Block Transfer Mode: Bit Bit Name Initial Value R/W Description 31 to 24 — All 0 — Reserved These bits are always read as 0 and cannot be modified. 23 to 16 Undefined 15 to 0 Undefined R/W Block Size These bits specify the block size (number of bytes or number of words) for block transfer. Setting H'01 specifies one as the block, while setting H'00 specifies the maximum block size, that is 256. The register value always indicates the specified block size.
Section 8 EXDMA Controller (EXDMAC) 8.3.4 EXDMA Mode Control Register (EDMDR) EDMDR controls EXDMAC operations. Bit Bit Name Initial Value R/W 15 EDA 0 R/(W) Description EXDMA Active Enables or disables data transfer on the corresponding channel. When this bit is set to 1, this indicates that an EXDMA operation is in progress. When auto request mode is specified (by bits MDS1 and MDS0), transfer processing begins when this bit is set to 1.
Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 14 BEF 0 R/(W)* Block Transfer Error Flag Flag that indicates the occurrence of an error during block transfer. If an NMI interrupt is generated during block transfer, the EXDMAC immediately terminates the EXDMA operation and sets this bit to 1. The address registers indicate the next transfer addresses, but the data for which transfer has been performed within the block size is lost.
Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 10 AMS 0 R/W Address Mode Select Selects single address mode or dual address mode. When single address mode is selected, the EDACK pin is valid. 0: Dual address mode 1: Single address mode 9 8 MDS1 MDS0 0 0 R/W R/W Mode Select 1 and 0 These bits specify the activation source, bus mode, and transfer mode.
Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 6 IRF 0 R/(W)* Interrupt Request Flag Flag indicating that an interrupt request has occurred and transfer has ended.
Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 3 DTSIZE 0 R/W Data Transmit Size Specifies the size of data to be transferred. 0: Byte-size 1: Word-size 2 BGUP 0 R/W Bus Give-Up When this bit is set to 1, the bus can be transferred to an internal bus master in burst mode or block transfer mode. This setting is ignored in normal mode and cycle steal mode.
Section 8 EXDMA Controller (EXDMAC) 8.3.5 EXDMA Address Control Register (EDACR) EDACR specifies address register incrementing/decrementing and use of the repeat area function. Bit Bit Name Initial Value R/W Description 15 14 SAT1 SAT0 0 0 R/W R/W Source Address Update Mode These bits specify incrementing/decrementing of the transfer source address (EDSAR). When an external device with DACK is designated as the transfer source in single address mode, the specification by these bits is ignored.
Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 12 11 10 9 8 SARA4 SARA3 SARA2 SARA1 SARA0 0 0 0 0 0 R/W R/W R/W R/W R/W Source Address Repeat Area These bits specify the source address (EDSAR) repeat area. The repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. A repeat area size of 2 bytes to 8 Mbytes can be specified. The setting interval is a power-of-two number of bytes.
Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 7 6 DAT1 DAT0 0 0 R/W R/W Destination Address Update Mode These bits specify incrementing/decrementing of the transfer destination address (EDDAR). When an external device with DACK is designated as the transfer destination in single address mode, the specification by these bits is ignored.
Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 4 3 2 1 0 DARA4 DARA3 DARA2 DARA1 DARA0 0 0 0 0 0 R/W R/W R/W R/W R/W Destination Address Repeat Area These bits specify the destination address (EDDAR) repeat area. The repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. A repeat area size of 2 bytes to 8 Mbytes can be specified. The setting interval is a power-of-two number of bytes.
Section 8 EXDMA Controller (EXDMAC) 8.4 Operation 8.4.1 Transfer Modes The transfer modes of the EXDMAC are summarized in table 8.2. Table 8.
Section 8 EXDMA Controller (EXDMAC) In block transfer mode, a transfer of the specified block size is executed in response to one transfer request. The block size can be from 1 to 256 bytes or words. Within a block, transfer can be performed at the same high speed as in block transfer mode. When the “no specification” setting (EDTCR = H'000000) is made for the number of transfers, the transfer counter is halted and there is no limit on the number of transfers, allowing transfer to be performed endlessly.
Section 8 EXDMA Controller (EXDMAC) EXDMA read cycle EXDMA write cycle φ Address bus EDSAR EDDAR RD WR ETEND Figure 8.2 Example of Timing in Dual Address Mode Single Address Mode: In single address mode, the EDACK signal is used instead of the source or destination address register to transfer data directly between an external device and external memory.
Section 8 EXDMA Controller (EXDMAC) External address bus External data bus Microcomputer External memory EXDMAC External device with DACK EDACK EDREQ Data flow Figure 8.3 Data Flow in Single Address Mode Rev.7.00 Mar.
Section 8 EXDMA Controller (EXDMAC) Transfer from external memory to external device with DACK EXDMA cycle φ Address bus EDSAR RD Address to external memory space RD signal to external memory space WR EDACK Data output from external memory Data bus ETEND Transfer from external device with DACK to external memory EXDMA cycle φ Address bus EDDAR Address to external memory space RD WR WR signal to external memory space EDACK Data output from external device with DACK Data bus ETEND Figure 8.
Section 8 EXDMA Controller (EXDMAC) 8.4.3 DMA Transfer Requests Auto Request Mode: In auto request mode, transfer request signals are automatically generated within the EXDMAC in cases where a transfer request signal is not issued from outside, such as in transfer between two memories, or between a peripheral module that is not capable of generating transfer requests and memory. In auto request mode, transfer is started when the EDA bit is set to 1 in EDMDR.
Section 8 EXDMA Controller (EXDMAC) takes back the bus, performs another transfer-unit transfer, and then releases the bus again. This procedure is repeated until the transfer end condition is satisfied. If a transfer request occurs in another channel during DMA transfer, the bus is temporarily released, then transfer is performed on the channel for which the transfer request was issued. If there is no external space bus request from another bus master, a one-cycle bus release interval is inserted.
Section 8 EXDMA Controller (EXDMAC) When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another bus master during burst transfer. If there is no bus request, burst transfer is executed even if the BGUP bit is set to 1. Figure 8.6 shows examples of the timing in burst mode.
Section 8 EXDMA Controller (EXDMAC) Bus cycle EXDMA transfer cycle Last EXDMA transfer cycle Read Read Write Write ETEND Transfer conditions: Dual address mode, auto request mode EDREQ EDRAK Bus cycle EXDMA EXDMA EDACK Transfer conditions: Single address mode, external request mode Figure 8.7 Examples of Timing in Normal Transfer Mode Block Transfer Mode: In block transfer mode, the number of bytes or words specified by the block size is transferred in response to one transfer request.
Section 8 EXDMA Controller (EXDMAC) Caution is required when setting the repeat area overflow interrupt of the repeat area function in block transfer mode. See section 8.4.6, Repeat Area Function, for details. Block transfer is aborted if an NMI interrupt is generated. See section 8.4.12, Ending DMA Transfer, for details. Figure 8.8 shows an example of DMA transfer timing in block transfer mode.
Section 8 EXDMA Controller (EXDMAC) The source address repeat area is specified by bits SARA4 to SARA0 in EDACR, and the destination address repeat area by bits DARA4 to DARA0 in EDACR. The size of each repeat area can be specified independently. When the address register value is the last address in the repeat area and repeat area overflow occurs, DMA transfer can be temporarily halted and an interrupt request sent to the CPU.
Section 8 EXDMA Controller (EXDMAC) mode, the block size must be a power of two, or alternatively, the address register value must be set so that the end of a block coincides with the end of the repeat area range. If repeat area overflow occurs while a block is being transferred in block transfer mode, the repeat interrupt request is held pending until the end of the block, and transfer overrun will occur. Figure 8.
Section 8 EXDMA Controller (EXDMAC) accessed next. Bits SAT1 and SAT0 in EDACR specify incrementing or decrementing. The address is fixed when SAT1 = 0, incremented when SAT1 = 1 and SAT0 = 0, and decremented when SAT1 = 1 and SAT0 = 1. The size of the increment or decrement is determined by the size of the data transferred.
Section 8 EXDMA Controller (EXDMAC) EXDMA Transfer Count Register (EDTCR): When a DMA transfer is performed, the value in EDTCR is decremented by 1. However, when the EDTCR value is 0, transfers are not counted and the EDTCR value does not change. EDTCR functions differently in block transfer mode. The upper 8 bits, EDTCR[23:16], are used to specify the block size, and their value does not change.
Section 8 EXDMA Controller (EXDMAC) EDTCR in normal transfer mode Before update 23 EDTCR Fixed 23 0 0 23 EDTCR After update 0 0 0 –1 23 1 to H'FFFFFF 0 0 to H'FFFFFE EDTCR in block transfer mode EDTCR Before update 23 16 15 Block 0 size EDTCR 23 16 15 Block 1 to H'FFFF size 0 0 Fixed –1 After update 23 16 15 Block 0 size 23 16 15 Block 0 to H'FFFE size 0 0 Figure 8.
Section 8 EXDMA Controller (EXDMAC) In burst mode, transfer is halted for up to three DMA transfers following the bus cycle in which 0 is written to the EDA bit. The EDA bit remains set to 1 from the time of the 0-write until the end of the last DMA cycle. Writes (except to the EDA bit) are prohibited to registers of a channel for which the EDA bit is set to 1. When changing register settings after a 0-write to the EDA bit, it is necessary to confirm that the EDA bit has been cleared to 0. Figure 8.
Section 8 EXDMA Controller (EXDMAC) IRF Bit in EDMDR: The IRF bit in EDMDR is set to 1 when an interrupt request source occurs. If the EDIE bit in EDMDR is 1 at this time, an interrupt is requested. The timing for setting the IRF bit to 1 is when the EDA bit in EDMDR is cleared to 0 and transfer ends following the end of the DMA transfer bus cycle in which the source generating the interrupt occurred.
Section 8 EXDMA Controller (EXDMAC) Channel 2 transfer Channel 3 transfer φ Channel 2 Address bus EXDMA control Idle Channel 2 Channel 2 Request cleared Channel 3 Request Selected held Bus release Channel 3 Bus release Channel 3 Request cleared Figure 8.
Section 8 EXDMA Controller (EXDMAC) Conditions (1) Channel 0: Auto request, cycle steal mode Channel 1: External request, cycle steal mode, low level activation Bus Channel 0 * Channel 0 * Channel 0 * Channel 1 * * Channel 1 Channel 0 EDA bit Channel 1/ EDREQ1 pin Conditions (2) Channel 1: External request, cycle steal mode, low level activation Channel 2: Auto request, cycle steal mode Bus Channel 2 * Channel 2 * Channel 1 * Channel 2 * Channel 1 * Channel 0 * Channel 0 * Chann
Section 8 EXDMA Controller (EXDMAC) 8.4.9 EXDMAC Bus Cycles (Dual Address Mode) Normal Transfer Mode (Cycle Steal Mode): Figure 8.15 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. After one byte or word has been transferred, the bus is released. While the bus is released, one CPU, DMAC, or DTC bus cycle is initiated.
Section 8 EXDMA Controller (EXDMAC) Normal Transfer Mode (Burst Mode): Figure 8.16 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (burst mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. In burst mode, one-byte or one-word transfers are executed continuously until transfer ends. Once burst transfer starts, requests from other channels, even of higher priority, are held pending until transfer ends.
Section 8 EXDMA Controller (EXDMAC) Block Transfer Mode (Cycle Steal Mode): Figure 8.17 shows an example of transfer when ETEND output is enabled, and word-size, block transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. One block is transferred in response to one transfer request, and after the transfer, the bus is released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.
Section 8 EXDMA Controller (EXDMAC) EDREQ Pin Falling Edge Activation Timing: Figure 8.18 shows an example of normal mode transfer activated by the EDREQ pin falling edge.
Section 8 EXDMA Controller (EXDMAC) One block transfer Bus release One block transfer DMA read DMA write Transfer source Transfer destination Bus release DMA read DMA write Bus release φ EDREQ Address bus DMA control Idle Read Channel Idle Read Write Request clearance period Request Minimum 3 cycles [1] Write Transfer source [2] [3] Idle Request clearance period Request Minimum 3 cycles [4] [5] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Transfer destination [6] [7] Acc
Section 8 EXDMA Controller (EXDMAC) EDREQ Pin Low Level Activation Timing: Figure 8.20 shows an example of normal mode transfer activated by the EDREQ pin low level.
Section 8 EXDMA Controller (EXDMAC) One block transfer Bus release One block transfer DMA read DMA write Transfer source Transfer destination Bus release DMA read DMA write Bus release φ EDREQ Address bus DMA control Read Idle Channel Write Transfer source Idle Read Write Request clearance period Request [2] [3] Minimum 3 cycles [4] [5] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Idle Request clearance period Request Minimum 3 cycles [1] Transfer destination [6] [7] Acce
Section 8 EXDMA Controller (EXDMAC) 8.4.10 EXDMAC Bus Cycles (Single Address Mode) Single Address Mode (Read): Figure 8.22 shows an example of transfer when ETEND output is enabled, and byte-size, single address mode transfer (read) is performed from external 8-bit, 2state access space to an external device. DMA read DMA read DMA read DMA read φ Address bus RD EDACK ETEND Bus release Bus release Bus release Bus release Last Bus release transfer cycle Figure 8.
Section 8 EXDMA Controller (EXDMAC) After one byte or word has been transferred in response to one transfer request, the bus is released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. Single Address Mode (Write): Figure 8.24 shows an example of transfer when ETEND output is enabled, and byte-size, single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space.
Section 8 EXDMA Controller (EXDMAC) DMA write DMA write DMA write φ Address bus HWR LWR EDACK ETEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 8.25 Example of Single Address Mode (Word Write) Transfer After one byte or word has been transferred in response to one transfer request, the bus is released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. Rev.7.00 Mar.
Section 8 EXDMA Controller (EXDMAC) EDREQ Pin Falling Edge Activation Timing: Figure 8.26 shows an example of single address mode transfer activated by the EDREQ pin falling edge.
Section 8 EXDMA Controller (EXDMAC) EDREQ Pin Low Level Activation Timing: Figure 8.27 shows an example of single address mode transfer activated by the EDREQ pin low level.
Section 8 EXDMA Controller (EXDMAC) 8.4.11 Examples of Operation Timing in Each Mode Auto Request/Cycle Steal Mode/Normal Transfer Mode: When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. There is a onecycle bus release interval between the end of a one-transfer-unit EXDMA cycle and the start of the next transfer.
Section 8 EXDMA Controller (EXDMAC) φ pin 1 bus cycle Bus cycle CPU cycle CPU operation External space EXDMA single transfer cycle CPU cycle External space Last transfer cycle EXDMA single transfer cycle CPU cycle EXDMA single transfer cycle External space CPU cycle External space EDACK ETEND Figure 8.
Section 8 EXDMA Controller (EXDMAC) Auto Request/Burst Mode/Normal Transfer Mode: When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. Once transfer is started, it continues (as a burst) until the transfer end condition is satisfied. If the BGUP bit is 1 in EDMDR, the bus is transferred in the event of a bus request from another bus master. Transfer requests for other channels are held pending until the end of transfer on the current channel. Figures 8.
Section 8 EXDMA Controller (EXDMAC) φ pin Last transfer cycle 1 bus cycle Bus cycle CPU operation EXDMA EXDMA EXDMA EXDMA EXDMA CPU cycle CPU cycle single cycle single cycle CPU cycle single cycle single cycle CPU cycle single cycle CPU cycle External space External space External space External space External space EDACK ETEND Figure 8.
Section 8 EXDMA Controller (EXDMAC) External Request/Cycle Steal Mode/Normal Transfer Mode: In external request mode, an EXDMA transfer cycle is started a minimum of three cycles after a transfer request is accepted. The next transfer request is accepted after the end of a one-transfer-unit EXDMA cycle. For external bus space CPU cycles, at least two bus cycles are generated before the next EXDMA cycle.
Section 8 EXDMA Controller (EXDMAC) φ pin EDREQ EDRAK 2 bus cycles Bus cycle CPU operation CPU cycle CPU cycle CPU cycle External space External space External space EXDMA single transfer cycle CPU cycle CPU cycle External space External space Last transfer cycle EXDMA single transfer cycle CPU cycle External space EDACK ETEND Figure 8.
Section 8 EXDMA Controller (EXDMAC) φ pin Original channel EDREQ Original channel EDRAK 1 cycle 3 cycles Bus cycle EXDMA transfer cycle Bus release EXDMA read 1 cycle Other channel transfer cycle EXDMA write Bus release EXDMA read EXDMA write Bus release Other channel EDREQ Other channel EDRAK Figure 8.
Rev.7.00 Mar. 18, 2009 page 412 of 1136 REJ09B0109-0700 EDA bit ETEND Bus cycle EDRAK EDREQ φ pin 1 Bus release EXDMA read EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write Last transfer in block Repeated 1-block-size transfer period Bus release 3 cycles EXDMA read EXDMA write Repeated EXDMA read 0 EXDMA write Bus release Last transfer cycle Last block Section 8 EXDMA Controller (EXDMAC) Figure 8.
ETEND EDACK Bus cycle EDRAK EDREQ φ pin Bus release EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle Last transfer in block Repeated 1-block-size transfer period Bus release 3 cycles EXDMA single transfer cycle Repeated EXDMA single transfer cycle Bus release Last transfer cycle Last block Section 8 EXDMA Controller (EXDMAC) Figure 8.
Rev.7.00 Mar.
External space CPU operation ETEND CPU cycle Bus cycle EDRAK EDREQ φ pin External space CPU cycle External space CPU cycle External space EXDMA read EXDMA write CPU cycle 1 bus cycle External space EXDMA read EXDMA write CPU cycle 1 bus cycle External space CPU cycle 1 bus cycle Repeated EXDMA read 1-block-size transfer period External space EXDMA read EXDMA write Last transfer in block CPU cycle External space CPU cycle Section 8 EXDMA Controller (EXDMAC) Figure 8.
Rev.7.00 Mar.
Other channel EDRAK Other channel EDREQ ETEND Bus cycle EDRAK EDREQ φ pin Bus release EXDMA read EXDMA write Repeated EXDMA read EXDMA write Last transfer in block 1-block-size transfer period Bus release Other channel EXDMA cycle Bus release EXDMA read EXDMA write Repeated EXDMA read EXDMA write Last transfer in block 1-block-size transfer period Section 8 EXDMA Controller (EXDMAC) Figure 8.
Section 8 EXDMA Controller (EXDMAC) 8.4.12 Ending DMA Transfer The operation for ending DMA transfer depends on the transfer end conditions. When DMA transfer ends, the EDA bit in EDMDR changes from 1 to 0, indicating that DMA transfer has ended. Transfer End by 1 → 0 Transition of EDTCR: When the value of EDTCR changes from 1 to 0, DMA transfer ends on the corresponding channel and the EDA bit in EDMDR is cleared to 0.
Section 8 EXDMA Controller (EXDMAC) In block transfer mode, operation is aborted even in the middle of a block-size transfer. As the transfer is halted midway through a block, the BEF bit in EDMDR is set to 1 to indicate that the block transfer was not carried out normally. When transfer is aborted, register values are retained, and as the address registers indicate the next transfer addresses, transfer can be resumed by setting the EDA bit to 1 in EDMDR.
Section 8 EXDMA Controller (EXDMAC) 8.5 Interrupt Sources EXDMAC interrupt sources are a transfer end indicated by the transfer counter, and repeat area overflow interrupts. Table 8.4 shows the interrupt sources and their priority order. Table 8.
Section 8 EXDMA Controller (EXDMAC) setting the EDA bit to 1 in EDMDR to perform transfer continuation processing. An example of the procedure for clearing the transfer end interrupt and restarting transfer is shown in figure 8.46.
Section 8 EXDMA Controller (EXDMAC) 8.6 Usage Notes 8.6.1 EXDMAC Register Access during Operation Except for clearing the EDA bit to 0 in EDMDR, settings should not be changed for a channel in operation (including the transfer standby state). Transfer must be disabled before changing a setting for an operational channel. 8.6.2 Module Stop State When the MSTP14 bit is set to 1 in MSTPCRH, the EXDMAC clock stops and the EXDMAC enters the module stop state.
Section 8 EXDMA Controller (EXDMAC) 8.6.4 Activation Source Acceptance At the start of activation source acceptance, low level sensing is used for both falling edge sensing and low level sensing on the EDREQ pin. Therefore, a request is accepted in the case of a low level at the EDREQ pin that occurs before execution of the EDMDR write for setting the transferenabled state.
Section 8 EXDMA Controller (EXDMAC) Rev.7.00 Mar.
Section 9 Data Transfer Controller (DTC) Section 9 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 9.1 shows a block diagram of the DTC. 9.1 Features • Transfer possible over any number of channels • Three transfer modes ⎯ Normal mode One operation transfers one byte or one word of data. Memory address is incremented or decremented by 1 or 2. From 1 to 65,536 transfers can be specified.
Section 9 Data Transfer Controller (DTC) Internal address bus On-chip RAM CPU interrupt request Register information MRA MRB CRA CRB DAR SAR DTC Control logic DTC activation request DTVECR Interrupt request DTCERA to DTCERH Interrupt controller Internal data bus Legend: MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERH DTVECR : DTC mode registers A and B : DTC transfer count registers A and B : DTC source address register : DTC destination address register : DTC enable registers A to H : DTC vector r
Section 9 Data Transfer Controller (DTC) 9.2 Register Descriptions DTC has the following registers. • DTC mode register A (MRA) • DTC mode register B (MRB) • DTC source address register (SAR) • DTC destination address register (DAR) • DTC transfer count register A (CRA) • DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU.
Section 9 Data Transfer Controller (DTC) Bit Bit Name Initial Value R/W Description 5 4 DM1 DM0 Undefined Undefined — — Destination Address Mode 1 and 0 These bits specify a DAR operation after a data transfer. 0×: DAR is fixed 10: DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 11: DAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) 3 2 MD1 MD0 Undefined Undefined — — DTC Mode These bits specify the DTC transfer mode.
Section 9 Data Transfer Controller (DTC) 9.2.2 DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit Bit Name Initial Value R/W 7 CHNE Undefined — Description DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, refer to section 9.5.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the activation source flag, and clearing of DTCER is not performed.
Section 9 Data Transfer Controller (DTC) 9.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL).
Section 9 Data Transfer Controller (DTC) 9.2.8 DTC Vector Register (DTVECR) DTVECR enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. Bit Bit Name Initial Value R/W Description 7 SWDTE 0 R/W DTC Software Activation Enable Setting this bit to 1 activates DTC. Only 1 can be written to this bit.
Section 9 Data Transfer Controller (DTC) 9.3 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI_0.
Section 9 Data Transfer Controller (DTC) Source flag cleared Clear controller Clear DTCER On-chip supporting module IRQ interrupt Interrupt request DTVECR Selection circuit Select Clear request DTC CPU Interrupt controller Interrupt mask Figure 9.2 Block Diagram of DTC Activation Source Control 9.4 Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF).
Section 9 Data Transfer Controller (DTC) Lower addresses 0 Start address of register information 1 2 MRA SAR MRB DAR 3 Register information CRB CRA Chain transfer MRA SAR MRB DAR CRB CRA Register information for second transfer in case of chain transfer Four bytes Figure 9.3 Correspondence between DTC Vector Address and Register Information DTC vector address Register information start address Register information Chain transfer Figure 9.
Section 9 Data Transfer Controller (DTC) Table 9.
Section 9 Data Transfer Controller (DTC) Origin of Activation Source Activation Source Vector Number DTC Vector Address DTCE* Priority TPU_3 TGI3A 56 H'0470 DTCED5 High TGI3B 57 H'0472 DTCED4 TGI3C 58 H'0474 DTCED3 TGI3D 59 H'0476 DTCED2 TGI4A 64 H'0480 DTCED1 TGI4B 65 H'0482 DTCED0 TGI5A 68 H'0488 DTCEE7 TGI5B 69 H'048A DTCEE6 CMIA0 72 H'0490 DTCEE3 CMIB0 73 H'0492 DTCEE2 CMIA1 76 H'0498 DTCEE1 CMIB1 77 H'049A DTCEE0 DMTEND0A 80 H'04A0 DTCEF7 DMTE
Section 9 Data Transfer Controller (DTC) 9.5 Operation The DTC stores register information in the on-chip RAM. When activated, the DTC reads register information that is already stored in the on-chip RAM and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to the onchip RAM. Pre-storage of register information in the on-chip RAM makes it possible to transfer data over any required number of channels.
Section 9 Data Transfer Controller (DTC) Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1? Yes No CHNS = 0? Yes Transfer counter = 0 or DISEL = 1? No Yes No Transfer counter = 0? Yes No DISEL = 1? Yes No Clear activation flag Clear DTCER End Interrupt exception handling Figure 9.5 Flowchart of DTC Operation Rev.7.00 Mar.
Section 9 Data Transfer Controller (DTC) Table 9.
Section 9 Data Transfer Controller (DTC) 9.5.1 Normal Mode In normal mode, one operation transfers one byte or one word of data. Table 9.4 lists the register function in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has ended, a CPU interrupt can be requested. Table 9.
Section 9 Data Transfer Controller (DTC) 9.5.2 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. Table 9.5 lists the register function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated.
Section 9 Data Transfer Controller (DTC) 9.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 9.6 lists the register function in block transfer mode. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored.
Section 9 Data Transfer Controller (DTC) 9.5.4 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 9.9 shows the operation of chain transfer. When activated, the DTC reads the register information start address stored at the vector address, and then reads the first register information at that start address.
Section 9 Data Transfer Controller (DTC) 9.5.5 Interrupt Sources An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control.
Section 9 Data Transfer Controller (DTC) φ DTC activation request DTC request Data transfer Vector read Read Write Read Write Address Transfer information read Transfer information write Figure 9.
Section 9 Data Transfer Controller (DTC) Table 9.7 DTC Execution Status Mode Vector Read I Register Information Data Read Read/Write K J Data Write L Internal Operations M Normal 1 6 1 1 3 Repeat 1 6 1 1 3 Block transfer 1 6 N N 3 Legend: N: Block size (initial setting of CRAH and CRAL) Table 9.
Section 9 Data Transfer Controller (DTC) 9.6 Procedures for Using DTC 9.6.1 Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the enable bits for the interrupt sources to be used as the activation sources to 1.
Section 9 Data Transfer Controller (DTC) 9.7 Examples of Use of the DTC 9.7.1 Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0).
Section 9 Data Transfer Controller (DTC) 9.7.2 Chain Transfer An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to NDR of the PPG is performed in the first half of the chain transfer, and normal mode transfer to the TPU’s TGR in the second half.
Section 9 Data Transfer Controller (DTC) 9.7.3 Chain Transfer when Counter = 0 By executing a second data transfer, and performing re-setting of the first data transfer, only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 9.13 shows the chain transfer when the counter value is 0. 1.
Section 9 Data Transfer Controller (DTC) Input circuit Input buffer First data transfer register information Chain transfer (counter = 0) Second data transfer register information Upper 8 bits of DAR Figure 9.13 Chain Transfer when Counter = 0 Rev.7.00 Mar.
Section 9 Data Transfer Controller (DTC) 9.7.4 Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0).
Section 9 Data Transfer Controller (DTC) 9.8.3 DTCE Bit Setting For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are disabled, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. 9.8.
Section 9 Data Transfer Controller (DTC) Rev.7.00 Mar.
Section 10 I/O Ports Section 10 I/O Ports Table 10.1 summarizes the port functions. The pins of each port also have other functions such as input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only ports do not have a DR or DDR register.
Section 10 I/O Ports Table 10.
Section 10 I/O Ports Mode 7 Port Description Mode 1*3 Mode 2*3 Mode 4 EXPE = 1 Port General I/O port 5 also functioning as interrupt inputs, A/D converter inputs, and SCI I/Os P53/ADTRG/IRQ3 Port General I/O port 6 also functioning as interrupt inputs, TMR I/Os, and DMAC I/Os P65/TMO1/DACK1/IRQ13 EXPE = 0 Input/ Output Type Schmitttriggered input when used as IRQ input P52/SCK2/IRQ2 P51/RxD2/IRQ1 P50/TxD2/IRQ0 Schmitttriggered input when used as IRQ input P64/TMO0/DACK0/IRQ12 P63/TMCI1/TEND1/IRQ1
Section 10 I/O Ports Mode 7 Port Description Mode 1*3 Mode 2*3 Mode 4 EXPE = 1 Port General I/O port A also functioning as address outputs EXPE = 0 PA7/A23/IRQ7 PA7/A23/IRQ7 PA7/IRQ7 PA6/A22/IRQ6 PA6/A22/IRQ6 PA6/IRQ6 PA5/A21/IRQ5 PA5/A21/IRQ5 PA5/IRQ5 A20/IRQ4 PA4/A20/IRQ4 PA4/IRQ4 A19 PA3/A19 PA3 A18 PA2/A18 PA2 A17 PA1/A17 PA1 A16 PA0/A16 PA0 Input/ Output Type Only PA4 to PA7 are Schmitttriggered input when used as IRQ input.
Section 10 I/O Ports Mode 7 Port Description Mode 1*3 Mode 2*3 Mode 4 EXPE = 1 Port General I/O port D also functioning as data I/Os Port General I/O port E also functioning as data I/Os Port General I/O port F also functioning as interrupt inputs and bus control I/Os D15 PD7 D14 PD6 D13 PD5 D12 PD4 D11 PD3 D10 PD2 D9 PD1 D8 PD0 PE7/D7 PE7 PE6/D6 PE6 PE5/D5 PE5 PE4/D4 PE4 PE3/D3 PE3 PE2/D2 PE2 PE1/D1 PE1 PE0/D0 PE0 PF7/φ PF7φ PF6/AS PF6 RD PF5 HWR PF4 PF3/LWR P
Section 10 I/O Ports Mode 7 Port Mode 1*3 Mode 2*3 Mode 4 Description EXPE = 1 Port General I/O port H also functioning as interrupt inputs and bus control I/Os EXPE = 0 PH3/CS7/(IRQ7)/OE/CKE*1 PH3/(IRQ7) PH2/CS6/(IRQ6) PH2/(IRQ6) PH1/CS5/RAS5/SDRAMφ*1 PH0/CS4/RAS4/WE *1 PH1/SDRAMφ*1 PH0 Input/ Output Type Only PH2 and PH3 are Schmitttriggered inputs when used as the IRQ input Notes: 1. Not supported by the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and H8S/2373. 2.
Section 10 I/O Ports 10.1.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit Bit Name Initial Value R/W Description 7 P17DR 0 R/W 6 P16DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W 10.1.3 Port 1 Register (PORT1) PORT1 shows the pin states. PORT1 cannot be modified.
Section 10 I/O Ports 10.1.4 Pin Functions Port 1 pins also function as the pins for PPG outputs, TPU I/Os, and EXDMAC outputs*. The correspondence between the register specification and the pin functions is shown below.
Section 10 I/O Ports Mode 7 (EXPE = 0) ⎯ EDRAKE TPU channel 2 settings (1) in table below (2) in table below P17DDR ⎯ 0 1 1 NDER15 ⎯ ⎯ 0 1 TIOCB2 output P17 input P17 output Pin function TIOCB2 input 2 TCLKD input* PO15 output *1 Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000, B'000, and B'01×× and IOB3 = 1. 2. TCLKD input when the setting for either TCR_0 or TCR_5 is TPSC2 to TPSC0 = B'111. TCLKD input when channels 2 and 4 are set to phase counting mode. 3.
Section 10 I/O Ports • P16/PO14/TIOCA2/EDRAK2*3 The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bit NDER14 in NDERH, bit EDRAKE in EDMDR_2 and bit P16DDR.
Section 10 I/O Ports Mode 7 (EXPE = 0) ⎯ EDRAKE TPU channel 2 settings (1) in table below (2) in table below P16DDR ⎯ 0 1 1 NDER14 ⎯ ⎯ 0 1 TIOCA2 output P16 input P16 output Pin function TIOCA2 input TPU channel 2 settings (2) MD3 to MD0 B'0000, B'01×× IOA3 to IOA0 (1) (2) (1) B'001× B'0010 PO14 output *1 (1) (2) B'0011 B'0000 B'0100 B'1××× B'0001 to B'0011 B'0101 to B'0111 B'××00 Other than B'××00 CCLR1, CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'10 B'10 Output function ⎯ Outp
Section 10 I/O Ports • P15/PO13/TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0, TCR_2, TCR_4, and TCR_5, bit NDER13 in NDERH, and bit P15DDR.
Section 10 I/O Ports • P14/PO12/TIOCA1 The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bit NDER12 in NDERH, and bit P14DDR.
Section 10 I/O Ports • P13/PO11/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, bit NDER11 in NDERH, and bit P13DDR.
Section 10 I/O Ports • P12/PO10/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH, and bit P12DDR.
Section 10 I/O Ports • P11/PO9/TIOCB0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER9 in NDERH, and bit P11DDR.
Section 10 I/O Ports • P10/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER8 in NDERH, and bit P10DDR.
Section 10 I/O Ports 10.2 Port 2 Port 2 is an 8-bit I/O port that also has other functions. The port 2 has the following registers. • Port 2 data direction register (P2DDR) • Port 2 data register (P2DR) • Port 2 register (PORT2) 10.2.1 Port 2 Data Direction Register (P2DDR) The individual bits of P2DDR specify input or output for the pins of port 2. P2DDR cannot be read; if it is, an undefined value will be read.
Section 10 I/O Ports 10.2.2 Port 2 Data Register (P2DR) P2DR stores output data for the port 2 pins. Bit Bit Name Initial Value R/W Description 7 P27DR 0 R/W 6 P26DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 P25DR 0 R/W 4 P24DR 0 R/W 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W 0 P20DR 0 R/W 10.2.3 Port 2 Register (PORT2) PORT2 shows the pin states. PORT2 cannot be modified.
Section 10 I/O Ports 10.2.4 Pin Functions Port 2 pins also function as PPG outputs, TPU I/Os, and interrupt inputs. The correspondence between the register specification and the pin functions is shown below. • P27/PO7/TIOCB5/(IRQ15) The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER7 in NDERL, bit P27DDR, and bit ITS15 in ITSR.
Section 10 I/O Ports • P26/PO6/TIOCA5/(IRQ14) The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER6 in NDERL, bit P26DDR, and bit ITS14 in ITSR.
Section 10 I/O Ports • P25/PO5/TIOCB4/(IRQ13) The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bit NDER5 in NDERL, bit P25DDR, and bit ITS13 in ITSR.
Section 10 I/O Ports • P24/PO4/TIOCA4/RxD4/(IRQ12) The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOA3 to IOA0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bit NDER4 in NDERL, bit RE in SCR of SCI_4, bit P24DDR, and bit ITS12 in ITSR.
Section 10 I/O Ports • P23/PO3/TIOCD3/TxD4/(IRQ11) The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL, bit TE in SCR of SCI_4, bit P23DDR, and bit ITS11 in ITSR.
Section 10 I/O Ports • P22/PO2/TIOCC3/(IRQ10) The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER2 in NDERL, bit P22DDR, and bit ITS10 in ITSR.
Section 10 I/O Ports • P21/PO1/TIOCB3/(IRQ9) The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL, bit P21DDR, and bit ITS9 in ITSR.
Section 10 I/O Ports • P20/PO0/TIOCA3/(IRQ8) The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL, bit P20DDR, and bit ITS8 in ITSR.
Section 10 I/O Ports 10.3 Port 3 Port 3 is a 6-bit I/O port that also has other functions. The port 3 has the following registers. • Port 3 data direction register (P3DDR) • Port 3 data register (P3DR) • Port 3 register (PORT3) • Port 3 open drain control register (P3ODR) • Port function control register 2(PFCR2) 10.3.1 Port 3 Data Direction Register (P3DDR) The individual bits of P3DDR specify input or output for the pins of port 3. P3DDR cannot be read; if it is, an undefined value will be read.
Section 10 I/O Ports 10.3.2 Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit Bit Name Initial Value R/W 7, 6 ⎯ All 0 ⎯ Description Reserved These bits are always read as 0 and cannot be modified. 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W 10.3.3 Output data for a pin is stored when the pin function is specified to a general purpose I/O. Port 3 Register (PORT3) PORT3 shows the pin states.
Section 10 I/O Ports 10.3.4 Port 3 Open Drain Control Register (P3ODR) P3ODR controls the output status for each port 3 pin. Bit Bit Name Initial Value R/W 7, 6 ⎯ All 0 ⎯ Description Reserved These bits are always read as 0 and cannot be modified. 5 P35ODR 0 R/W 4 P34ODR 0 R/W 3 P33ODR 0 R/W 2 P32ODR 0 R/W 1 P31ODR 0 R/W 0 P30ODR 0 R/W Rev.7.00 Mar.
Section 10 I/O Ports 10.3.5 Port Function Control Register 2 (PFCR2) P3ODR controls the I/O port. Bit Bit Name Initial Value R/W 7 to 4 ⎯ All 0 ⎯ 3 ASOE Description Reserved These bits are always read as 0 and cannot be modified. 1 R/W AS Output Enable Selects to enable or disable the AS output pin. 0: PF6 is designated as I/O port 1: PF6 is designated as AS output pin 2 LWROE 1 R/W LWR Output Enable Selects to enable or disable the LWR output pin.
Section 10 I/O Ports 10.3.6 Pin Functions Port 3 pins also function as the pins for SCI I/Os, I2C output, and a bus control signal output. The correspondence between the register specification and the pin functions is shown below. • P35/SCK1/SCL0/(OE)/(CKE*3) The pin function is switched as shown below according to the combination of the ICE bit in ICCRA of I2C_0, C/A bit in SMR of SCI_1, bits CKE0 and CKE1 in SCR, bits OEE and RMTS2 to RMTS0 in DRAMCR, bit OES in PFCR2, and bit P35DDR.
Section 10 I/O Ports Mode 7 (EXPE = 0) OEE ⎯ OES ⎯ SDRAM space ⎯ ICE 0 CKE1 C/A ⎯ 1 ⎯ ⎯ 1 ⎯ ⎯ ⎯ 0 CKE0 0 0 1 ⎯ ⎯ ⎯ ⎯ P35 input P35 1 output* SCK1 1 output* SCK1 1 output* SCK1 input SCL0 2 I/O* P35DDR Pin function 1 1 0 Notes: 1. NMOS open-drain output when P35ODR = 1. 2. NMOS open-drain output regardless of P35ODR. 3. Not used in the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and H8S/2373.
Section 10 I/O Ports • P33/RxD1/SCL1 The pin function is switched as shown below according to the combination of bit ICE in ICCRA of I2C_0, bit RE in SCR of SCI_1 and bit P33DDR. ICE 0 RE 1 0 P33DDR Pin function 1 ⎯ 0 1 ⎯ ⎯ P33 input 1 P33 output* RxD1 input SCL1 I/O* 2 Notes: 1. NMOS open-drain output when P33ODR = 1. 2. NMOS open-drain output regardless of P33ODR.
Section 10 I/O Ports • P30/TxD0/IrTxD The pin function is switched as shown below according to the combination of bit TE in SCR of SCI_0 and bit P30DDR. TE 0 0 1 ⎯ P30 input P30 output* RxD0/IrRxD output* P30DDR Pin function Note: NMOS open-drain output when P30ODR = 1. * 10.4 1 Port 4 Port 4 is an 8-bit input-only port. Port 4 has the following register. • Port 4 register (PORT4) 10.4.1 Port 4 Register (PORT4) PORT4 is an 8-bit read-only register that shows port 4 pin states.
Section 10 I/O Ports 10.4.2 Pin Functions Port 4 also functions as the pins for A/D converter analog input and D/A converter analog output. The correspondence between pins are as follows. • P47/AN7/DA1* Pin function AN7 input DA1 output Note: * Not available for the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R. • P46/AN6/DA0* Pin function AN6 input DA0 output Note: * Not available for the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
Section 10 I/O Ports 10.5 Port 5 Port 5 is a 4-bit I/O port. The port 5 has the following registers. • Port 5 data direction register (P5DDR) • Port 5 data register (P5DR) • Port 5 register (PORT5) 10.5.1 Port 5 Data Direction Register (P5DDR) The individual bits of P5DDR specify input or output for the pins of port 5. P5DDR cannot be read; if it is, an undefined value will be read.
Section 10 I/O Ports 10.5.3 Port 5 Register (PORT5) PORT5 shows the pin states. PORT5 cannot be modified. Bit Bit Name 7to 4 ⎯ Initial Value R/W Description Undefined R Reserved Undefined values are read from these bits. 3 P53 ⎯* R 2 P52 ⎯* R 1 P51 ⎯* R 0 P50 ⎯* R Note: * 10.5.4 If bits P53 to P50 are read while P5DDR bits are set to 1, the P5DR values are read. If a port 5 read is performed while P5DDR bits are cleared to 0, the pin states are read.
Section 10 I/O Ports • P52/SCK2/IRQ2 The pin function is switched as shown below according to the combination of bit C/A in SMR of SCI_2, bits CKE0 and CKE1 in SCR, bit ITS2 in ITSR, and bit P52DDR. CKE1 0 C/A 1 0 CKE0 0 P52DDR Pin function 1 1 ⎯ ⎯ ⎯ 0 1 ⎯ ⎯ ⎯ P52 input P52 output SCK2 output SCK2 output SCK2 input IRQ2 interrupt input* Note: * IRQ2 input when ITS2 = 0.
Section 10 I/O Ports 10.6 Port 6 Port 6 is a 6-bit I/O port that also has other functions. The port 6 has the following registers. • Port 6 data direction register (P6DDR) • Port 6 data register (P6DR) • Port 6 register (PORT6) 10.6.1 Port 6 Data Direction Register (P6DDR) The individual bits of P6DDR specify input or output for the pins of port 6. P6DDR cannot be read; if it is, an undefined value will be read.
Section 10 I/O Ports 10.6.2 Port 6 Data Register (P6DR) P6DR stores output data for the port 6 pins. Bit Bit Name Initial Value R/W 7, 6 ⎯ All 0 ⎯ Description Reserved These bits are always read as 0 and cannot be modified. 5 P65DR 0 R/W 4 P64DR 0 R/W 3 P63DR 0 R/W 2 P62DR 0 R/W 1 P61DR 0 R/W 0 P60DR 0 R/W 10.6.3 An output data for a pin is stored when the pin function is specified to a general purpose I/O. Port 6 Register (PORT6) PORT6 shows the pin states.
Section 10 I/O Ports 10.6.4 Pin Functions Port 6 pins also function as 8-bit timer I/Os, interrupt inputs, and DMAC I/Os. The correspondence between the register specification and the pin functions is shown below. • P65/TMO1/DACK1/IRQ13 The pin function is switched as shown below according to the combination of bit SAE1 in DMABCRH of the DMAC, bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit P65DDR, and bit ITS13 in ITSR.
Section 10 I/O Ports • P63/TMCI1/TEND1/IRQ11 The pin function is switched as shown below according to the combination of bit TEE1 in DMATCR of the DMAC, bit P63DDR, and bit ITS11 in ITSR. TEE1 P63DDR Pin function 0 1 0 1 ⎯ P63 input P63 output TEND1 output IRQ11 interrupt input* 2 TMCI1 input* 1 Notes: 1. IRQ11 interrupt input when ITS11 = 0. 2.
Section 10 I/O Ports • P61/TMRI1/DREQ1/IRQ9 The pin function is switched as shown below according to the combination of bit P61DDR and bit ITS9 in ITSR. P61DDR Pin function 0 1 P61 input P61 output 1 TMRI1 input* DREQ1 input IRQ9 interrupt input* 2 Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits in TCR_1 should be set to 1. 2. IRQ9 interrupt input when ITS9 = 0.
Section 10 I/O Ports 10.7 Port 8 Port 8 is a 6-bit I/O port that also has other functions. The port 8 has the following registers. • Port 8 data direction register (P8DDR) • Port 8 data register (P8DR) • Port 8 register (PORT8) 10.7.1 Port 8 Data Direction Register (P8DDR) The individual bits of P8DDR specify input or output for the pins of port 8. P8DDR cannot be read; if it is, an undefined value will be read.
Section 10 I/O Ports 10.7.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins. Bit Bit Name Initial Value R/W 7, 6 ⎯ 0 ⎯ Description Reserved These bits are always read as 0 and cannot be modified. 5 P85DR 0 R/W 4 P84DR 0 R/W 3 P83DR 0 R/W 2 P82DR 0 R/W 1 P81DR 0 R/W 0 P80DR 0 R/W 10.7.3 Output data for a pin is stored when the pin function is specified to a general purpose I/O. Port 8 Register (PORT8) PORT8 shows the pin states.
Section 10 I/O Ports 10.7.4 Pin Functions Port 8 pins also function as SCI I/Os, interrupt inputs, and EXDMAC I/Os. The correspondence between the register specification and the pin functions is shown below. • P85/EDACK3*/(IRQ5)/SCK3 The pin function is switched as shown below according to the combination of bit AMS in EDMDR_3 of the EXDMAC, bit C/A in SMR in SCI_3, bit P85DDR, and bit ITS5 in ITSR. Note: * Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
Section 10 I/O Ports • P84/EDACK2*/(IRQ4) The pin function is switched as shown below according to the combination of bit AMS in EDMDR_2 of the EXDMAC, bit P84DDR, and bit ITS4 in ITSR. Note: * Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R. Modes 1, 2, 4, 7 (EXPE = 1) AMS 0 0 1 ⎯ P84 input P84 input/output EDACK2 output P84DDR Pin function 1 IRQ4 interrupt input* Note: * IRQ4 input when ITS4 = 1.
Section 10 I/O Ports Mode 7 (EXPE = 0) ⎯ ETENDE RE 0 P83DDR 0 Pin function 1 ⎯ 1 P83 input P83 output RXD3 input IRQ3 interrupt input* Note: * IRQ3 input when ITS3 = 1. • P82/ETEND2*/(IRQ2) The pin function is switched as shown below according to the combination of bit ETENDE in EDMDR_2 of the EXDMAC, bit P82DDR, and bit ITS2 in ITSR. Note: * Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
Section 10 I/O Ports • P81/EDREQ3*/(IRQ1)/TxD3 The pin function is switched as shown below according to the combination of bit TE in SCR of SCI_3, bit P81DDR and bit ITS1 in ITSR. Note: * Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R. TE 0 0 1 ⎯ P81 input P81 output TxD3 output P81DDR Pin function 1 EDREQ3 input IRQ1 interrupt input* Note: * IRQ1 input when ITS1 = 1.
Section 10 I/O Ports 10.8 Port 9 Port 9 is an 8-bit input-only port. Port 4 has the following register. • Port 9 register (PORT4) 10.8.1 Port 9 Register (PORT9) PORT9 is an 8-bit read-only register that shows port 4 pin states. PORT9 cannot be modified. Bit Bit Name Initial Value R/W Description 7 P97 ⎯* R 6 P96 ⎯* R The pin states are always read when a port 9 read is performed.
Section 10 I/O Ports 10.8.2 Pin Functions Port 9 also functions as the pins for A/D converter analog input and D/A converter analog output. The correspondence between pins are as follows. • P97/AN15/DA5* Pin function AN15 input DA5 output Note: * Not available for the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R. • P96/AN14/DA4* Pin function AN14 input DA4 output Note: * Not available for the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
Section 10 I/O Ports 10.9 Port A Port A is an 8-bit I/O port that also has other functions. The port A has the following registers. • Port A data direction register (PADDR) • Port A data register (PADR) • Port A register (PORTA) • Port A pull-up MOS control register (PAPCR) • Port A open-drain control register (PAODR) • Port function control register 1 (PFCR1) 10.9.1 Port A Data Direction Register (PADDR) The individual bits of PADDR specify input or output for the pins of port A.
Section 10 I/O Ports 10.9.2 Port A Data Register (PADR) PADR stores output data for the port A pins. Bit Bit Name Initial Value R/W Description 7 PA7DR 0 R/W 6 PA6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 PA5DR 0 R/W 4 PA4DR 0 R/W 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 PA0DR 0 R/W 10.9.3 Port A Register (PORTA) PORTA shows port A pin states. PORTA cannot be modified.
Section 10 I/O Ports 10.9.4 Port A Pull-Up MOS Control Register (PAPCR) PAPCR controls the input pull-up MOS function. Bits 7 to 5 are valid in modes 1 and 2 and all the bits are valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description 7 PA7PCR 0 R/W 6 PA6PCR 0 R/W When PADDR = 0 (input port), setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.
Section 10 I/O Ports Bit Bit Name Initial Value R/W Description 7 A23E 1 R/W Address 23 Enable Enables or disables output for address output 23 (A23). 0: DR output when PA7DDR = 1 1: A23 output when PA7DDR = 1 6 A22E 1 R/W Address 22 Enable Enables or disables output for address output 22 (A22). 0: DR output when PA6DDR = 1 1: A22 output when PA6DDR = 1 5 A21E 1 R/W Address 21 Enable Enables or disables output for address output 21 (A21).
Section 10 I/O Ports 10.9.7 Pin Functions Port A pins also function as the pins for address outputs and interrupt inputs. The correspondence between the register specification and the pin functions is shown below. • PA7/A23/IRQ7, PA6/A22/IRQ6, PA5/A21/IRQ5 The pin function is switched as shown below according to the operating mode, bit EXPE, bits A23E to A21E, bits ITS7 to ITS5 in ITSR, and bit PADDR.
Section 10 I/O Ports • PA3/A19, PA2/A18, PA1/A17, PA20/A16 The pin function is switched as shown below according to the operating mode, bit EXPE, bits A19E to A16E, and bit PADDR. Operating mode 1, 2 EXPE ⎯ AxxE ⎯ 4 7 ⎯ 0 0 1 ⎯ 1 0 1 PAnDDR ⎯ 0 1 0 1 0 1 0 1 0 1 Pin function Address output PAn input PAn output PAn input Address output PAn input PAn output PAn input PAn output PAn input Address output xx = 19 to 16, n = 3 to 0 10.9.
Section 10 I/O Ports 10.10 Port B Port B is an 8-bit I/O port that also has other functions. The port B has the following registers. • Port B data direction register (PBDDR) • Port B data register (PBDR) • Port B register (PORTB) • Port B pull-up MOS control register (PBPCR) 10.10.1 Port B Data Direction Register (PBDDR) The individual bits of PBDDR specify input or output for the pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.
Section 10 I/O Ports 10.10.2 Port B Data Register (PBDR) PBDR is stores output data for the port B pins. Bit Bit Name Initial Value R/W Description 7 PB7DR 0 R/W 6 PB6DR 0 R/W An output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 PB5DR 0 R/W 4 PB4DR 0 R/W 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 PB0DR 0 R/W 10.10.3 Port B Register (PORTB) PORTB shows port B pin states. PORTB cannot be modified.
Section 10 I/O Ports 10.10.4 Port B Pull-Up MOS Control Register (PBPCR) PBPCR controls the on/off state of input pull-up MOS of port B. PBPCR is valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description 7 PB7PCR 0 R/W 6 PB6PCR 0 R/W When PBDDR = 0 (input port), setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 5 PB5PCR 0 R/W 4 PB4PCR 0 R/W 3 PB3PCR 0 R/W 2 PB2PCR 0 R/W 1 PB1PCR 0 R/W 0 PB0PCR 0 R/W 10.10.
Section 10 I/O Ports 10.10.6 Port B Input Pull-Up MOS States Port B has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in modes 4 and 7. Input pull-up MOS can be specified as on or off on a bit-by-bit basis. In modes 4 and 7, when a PBDDR bit is cleared to 0, setting the corresponding PBPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.3 summarizes the input pull-up MOS states. Table 10.
Section 10 I/O Ports 10.11 Port C Port C is an 8-bit I/O port that also has other functions. The port C has the following registers. • Port C data direction register (PCDDR) • Port C data register (PCDR) • Port C register (PORTC) • Port C pull-up MOS control register (PCPCR) 10.11.1 Port C Data Direction Register (PCDDR) The individual bits of PCDDR specify input or output for the pins of port C. PCDDR cannot be read; if it is, an undefined value will be read.
Section 10 I/O Ports 10.11.2 Port C Data Register (PCDR) PCDR stores output data for the port C pins. Bit Bit Name Initial Value R/W Description 7 PC7DR 0 R/W 6 PC6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 PC5DR 0 R/W 4 PC4DR 0 R/W 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W 0 PC0DR 0 R/W 10.11.3 Port C Register (PORTC) PORTC is shows port C pin states. PORTC cannot be modified.
Section 10 I/O Ports 10.11.4 Port C Pull-Up MOS Control Register (PCPCR) PCPCR controls the on/off state of input pull-up MOS of port C. PCPCR is valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description 7 PC7PCR 0 R/W 6 PC6PCR 0 R/W When PCDDR = 0 (input port), setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 5 PC5PCR 0 R/W 4 PC4PCR 0 R/W 3 PC3PCR 0 R/W 2 PC2PCR 0 R/W 1 PC1PCR 0 R/W 0 PC0PCR 0 R/W 10.11.
Section 10 I/O Ports 10.11.6 Port C Input Pull-Up MOS States Port C has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in modes 4 and 7. Input pull-up MOS can be specified as on or off on a bit-by-bit basis. In modes 4 and 7, when a PCDDR bit is cleared to 0, setting the corresponding PCPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.4 summarizes the input pull-up MOS states. Table 10.
Section 10 I/O Ports 10.12 Port D Port D is an 8-bit I/O port that also has other functions. The port D has the following registers. • Port D data direction register (PDDDR) • Port D data register (PDDR) • Port D register (PORTD) • Port D pull-up MOS control register (PDPCR) 10.12.1 Port D Data Direction Register (PDDDR) The individual bits of PDDDR specify input or output for the pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.
Section 10 I/O Ports 10.12.2 Port D Data Register (PDDR) PDDR stores output data for the port D pins. Bit Bit Name Initial Value R/W Description 7 PD7DR 0 R/W 6 PD6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 PD5DR 0 R/W 4 PD4DR 0 R/W 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W 0 PD0DR 0 R/W 10.12.3 Port D Register (PORTD) PORTD shows port D pin states. PORTD cannot be modified.
Section 10 I/O Ports 10.12.4 Port D Pull-up Control Register (PDPCR) PDPCR controls on/off states of the input pull-up MOS of port D. PDPCR is valid in mode 7. Bit Bit Name Initial Value R/W 7 PD7PCR 0 R/W 6 PD6PCR 0 R/W 5 PD5PCR 0 R/W 4 PD4PCR 0 R/W 3 PD3PCR 0 R/W 2 PD2PCR 0 R/W 1 PD1PCR 0 R/W 0 PD0PCR 0 R/W Description When PDDDR = 0 (input port), the input pull-up MOS of the input pin is on when the corresponding bit is set to 1. 10.12.
Section 10 I/O Ports 10.12.6 Port D Input Pull-Up MOS States Port D has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in mode 7. Input pull-up MOS can be specified as on or off on a bit-by-bit basis. In mode 7, when a PDDDR bit is cleared to 0, setting the corresponding PDPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.5 summarizes the input pull-up MOS states. Table 10.
Section 10 I/O Ports 10.13 Port E Port E is an 8-bit I/O port that also has other functions. The port E has the following registers. • Port E data direction register (PEDDR) • Port E data register (PEDR) • Port E register (PORTE) • Port E pull-up MOS control register (PEPCR) 10.13.1 Port E Data Direction Register (PEDDR) The individual bits of PEDDR specify input or output for the pins of port E. PEDDR cannot be read; if it is, an undefined value will be read.
Section 10 I/O Ports 10.13.2 Port E Data Register (PEDR) PEDR stores output data for the port E pins. Bit Bit Name Initial Value R/W Description 7 PE7DR 0 R/W 6 PE6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 PE5DR 0 R/W 4 PE4DR 0 R/W 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 PE0DR 0 R/W 10.13.3 Port E Register (PORTE) PORTE shows port E pin states. PORTE cannot be modified.
Section 10 I/O Ports 10.13.4 Port E Pull-up Control Register (PEPCR) PEPCR controls on/off states of the input pull-up MOS of port E. PEPCR is valid in 8-bit bus mode. Bit Bit Name Initial Value R/W 7 PE7PCR 0 R/W 6 PE6PCR 0 R/W 5 PE5PCR 0 R/W 4 PE4PCR 0 R/W 3 PE3PCR 0 R/W 2 PE2PCR 0 R/W 1 PE1PCR 0 R/W 0 PE0PCR 0 R/W Description When PEDDR = 0 (input port), the input pull-up MOS of the input pin is on when the corresponding bit is set to 1. 10.13.
Section 10 I/O Ports 10.13.6 Port E Input Pull-Up MOS States Port E has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in 8-bit bus mode. Input pull-up MOS can be specified as on or off on a bit-by-bit basis. In 8-bit bus mode, when a PEDDR bit is cleared to 0, setting the corresponding PEPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.6 summarizes the input pull-up MOS states. Table 10.
Section 10 I/O Ports 10.14.1 Port F Data Direction Register (PFDDR) The individual bits of PFDDR specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
Section 10 I/O Ports 10.14.2 Port F Data Register (PFDR) PFDR stores output data for the port F pins. Bit Bit Name Initial Value R/W Description 7 PF7DR 0 R/W 6 PF6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 PF5DR 0 R/W 4 PF4DR 0 R/W 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W 0 PF0DR 0 R/W 10.14.3 Port F Register (PORTF) PORTF shows port F pin states. PORTF cannot be modified.
Section 10 I/O Ports 10.14.4 Pin Functions Port F pins also function as the pins for external interrupt inputs, bus control signal I/Os, and system clock outputs (φ). The correspondence between the register specification and the pin functions is shown below. • PF7/φ The pin function is switched as shown below according to bit PF7DDR.
Section 10 I/O Ports • PF4/HWR The pin function is switched as shown below according to the operating mode, bit EXPE, and bit PF4DDR. Operating mode 1, 2, 4 7 EXPE ⎯ PF4DDR ⎯ 0 1 ⎯ HWR output PF4 input PF4 output HWR output Pin function 0 1 • PF3/LWR The pin function is switched as shown below according to the operating mode, bit EXPE, bit LWROE, and bit PF3DDR.
Section 10 I/O Ports • PF2/LCAS/IRQ15/DQML*2 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, bits ABW5 to ABW2 in ABWCR, and bit PF2DDR.
Section 10 I/O Ports • PF1/UCAS/IRQ14/DQMU*2 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, and bit PF1DDR.
Section 10 I/O Ports 10.15 Port G Port G is a 7-bit I/O port that also has other functions. The port G has the following registers. • Port G data direction register (PGDDR) • Port G data register (PGDR) • Port G register (PORTG) • Port Function Control Register 0 (PFCR0) 10.15.1 Port G Data Direction Register (PGDDR) The individual bits of PGDDR specify input or output for the pins of port G. PGDDR cannot be read; if it is, an undefined value will be read.
Section 10 I/O Ports 10.15.2 Port G Data Register (PGDR) PGDR stores output data for the port G pins. Bit Bit Name Initial Value R/W 7 ⎯ 0 ⎯ Description Reserved This bit is always read as 0, and cannot be modified. 6 PG6DR 0 R/W 5 PG5DR 0 R/W 4 PG4DR 0 R/W 3 PG3DR 0 R/W 2 PG2DR 0 R/W 1 PG1DR 0 R/W 0 PG0DR 0 R/W An output data for a pin is stored when the pin function is specified to a general purpose I/O. 10.15.3 Port G Register (PORTG) PORTG shows port G pin states.
Section 10 I/O Ports 10.15.4 Port Function Control Register 0 (PFCR0) PFCR0 performs I/O port control. Bit Bit Name Initial Value R/W Description 7 CS7E 1 R/W CS7 to CS0 Enable 6 CS6E 1 R/W 5 CS5E 1 R/W These bits enable or disable the corresponding CSn output. 4 CS4E 1 R/W 3 CS3E 1 R/W 2 CS2E 1 R/W 1 CS1E 1 R/W 0 CS0E 1 R/W 0: Pin is designated as I/O port 1: Pin is designated as CSn output pin (n = 7 to 0) 10.15.
Section 10 I/O Ports • PG5/BACK The pin function is switched as shown below according to the operating mode, bit EXPE, bit BRLE, and bit PG5DDR. Operating mode 1, 2, 4 7 ⎯ EXPE BRLE 0 0 0 1 ⎯ 0 PG5 input PG5 output BACK output PG5 input PG5DDR Pin function 1 ⎯ 1 0 1 0 PG5 PG5 input output 1 1 ⎯ PG5 output BACK output • PG4/BREQO The pin function is switched as shown below according to the operating mode, bit EXPE, bit BRLE, bit BREQO, and bit PG4DDR.
Section 10 I/O Ports • PG3/CS3/RAS3/CAS* The pin function is switched as shown below according to the operating mode, bit PG3DDR, bit CS3E, and bits RMTS2 to RMTS0.
Section 10 I/O Ports • PG1/CS1, PG0/CS0 The pin function is switched as shown below according to the operating mode, bit EXPE, bit CSnE, and bit PGnDDR. Operating mode 1, 2, 4 7 ⎯ EXPE CSnE 0 0 PGnDDR Pin function 1 ⎯ 1 0 1 0 1 0 1 0 1 0 1 0 1 PG2 input PG2 output PG2 input CSn output PG2 input PG2 output PG2 input PG2 output PG2 input CSn output (n =1 or 0) 10.16 Port H Port H is a 4-bit I/O port that also has other functions. The port H has the following registers.
Section 10 I/O Ports Bit Bit Name Initial Value R/W Description 7 to 4 — All 0 — Reserved 3 PH3DDR 0 W • Modes 1*3, 2*3, 4 and 7 (when EXPE = 1) 2 PH2DDR 0 W 1 PH1DDR 0 W 0 PH0DDR 0 W When the OE output enable bit (OEE) and OE output select bit (OES) are set to 1, pin PH3 functions as the OE output pin. Otherwise, when bit CS7E is set to 1, pin PH3 functions as a CS output pin when the corresponding PH3DDR bit is set to 1, and as an input port when the bit is cleared to 0.
Section 10 I/O Ports 10.16.2 Port H Data Register (PHDR) PHDR stores output data for the port H pins. Bit Bit Name Initial Value R/W 7 to 4 ⎯ All 0 ⎯ 3 PH3DR 0 R/W 2 PH2DR 0 R/W 1 PH1DR 0 R/W 0 PH0DR 0 R/W Description Reserved These bits are reserved; they are always read as 0 and cannot be modified. Output data for a pin is stored when the pin function is specified to a general purpose I/O. 10.16.3 Port H Register (PORTH) PORTH shows port H pin states. PORTH cannot be modified.
Section 10 I/O Ports 10.16.4 Pin Functions Port H pins also function as bus control signal I/Os and interrupt inputs. The correspondence between the register specification and the pin functions is shown below. Note: Only modes 1 and 2 are supported on ROM-less versions. • PH3/CS7/OE/CKE*2/(IRQ7) The pin function is switched as shown below according to the operating mode, bit EXPE, bit OEE, bit OES, bit CS7E, and bit PH3DDR.
Section 10 I/O Ports • PH1/CS5/RAS5/SDRAMφ*2 The pin function is switched as shown below according to the operating mode, DCTL pin, bit EXPE, bit CS5E, bits RMTS2 to RMTS0, and bit PH1DDR.
Section 11 16-Bit Timer Pulse Unit (TPU) Section 11 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 11.1 and figure 11.1, respectively. 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 DTC TGR activation compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture DMAC TGRA activation compare match or input capture TGRA compare match or input capture TGRA compare match or input capture TGRA compare match or input capture TGRA
TGRD TGRB TGRC TGRB A/D conversion start request signal TGRD TGRB TGRB TGRB PPG output trigger signal Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Timer counter Figure 11.1 Block Diagram of TPU Rev.7.00 Mar.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.2 Input/Output Pins Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3 Register Descriptions The TPU has the following registers in each channel.
Section 11 16-Bit Timer Pulse Unit (TPU) • Timer interrupt enable register_3 (TIER_3) • Timer status register_3 (TSR_3) • Timer counter_3 (TCNT_3) • Timer general register A_3 (TGRA_3) • Timer general register B_3 (TGRB_3) • Timer general register C_3 (TGRC_3) • Timer general register D_3 (TGRD_3) • Timer control register_4 (TCR_4) • Timer mode register_4 (TMDR_4) • Timer I/O control register _4 (TIOR_4) • Timer interrupt enable register_4 (TIER_4) • Timer status register_4 (TSR_4) • Timer counter_4 (TCNT_
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.1 Timer Control Register (TCR) The TCR registers control the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only when TCNT operation is stopped. Bit Bit Name Initial Value R/W Description 7 6 5 CCLR2 CCLR1 CCLR0 0 0 0 R/W R/W R/W Counter Clear 2 to 0 4 3 CKEG1 CKEG0 0 0 R/W R/W Clock Edge 1 and 0 These bits select the TCNT counter clearing source.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.5 TPSC2 to TPSC0 (Channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input 1 1 0 1 Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.2 Timer Mode Register (TMDR) TMDR registers are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped. Bit Bit Name Initial Value R/W Description 7, 6 — All 1 — Reserved These bits are always read as 1 and cannot be modified.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.11 MD3 to MD0 Bit 3 1 MD3* Bit 2 2 MD2* Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 × ⎯ 1 1 0 1 1 × × Legend: ×: Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3.
Section 11 16-Bit Timer Pulse Unit (TPU) TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Bit Bit Name Initial Value R/W Description 7 6 5 4 IOB3 IOB2 IOB1 IOB0 0 0 0 0 R/W R/W R/W R/W I/O Control B3 to B0 3 2 1 0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 R/W R/W R/W R/W I/O Control A3 to A0 Specify the function of TGRB. For details, see tables 11.12, 11.14, 11.15, 11.16, 11.18, and 11.19. Specify the function of TGRA. For details, see tables 11.20, 11.22, 11.23, 11.24, 11.26, and 11.27.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.4 Timer Interrupt Enable Register (TIER) TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TTGE 0 R/W A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match.
Section 11 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W Description 2 TGIEC 0 R/W TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.5 Timer Status Register (TSR) TSR registers indicate the status of each channel. The TPU has six TSR registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TCFD 1 R Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified.
Section 11 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W Description 3 TGFD 0 R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.
Section 11 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W Description 1 TGFB 0 R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, or in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 11.3.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.9 Timer Synchronous Register (TSYR) TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Bit Name Initial value R/W Description 7, 6 — — R/W Reserved 5 4 3 2 1 0 SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W The write value should always be 0.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.4 Operation 11.4.1 Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting.
Section 11 16-Bit Timer Pulse Unit (TPU) 2. Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (changes from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt.
Section 11 16-Bit Timer Pulse Unit (TPU) TCNT value TGR Counter cleared by TGR compare match H'0000 Time CST bit Flag cleared by software or DTC activation TGF Figure 11.4 Periodic Counter Operation Rev.7.00 Mar.
Section 11 16-Bit Timer Pulse Unit (TPU) Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match. 1. Example of setting procedure for waveform output by compare match Figure 11.5 shows an example of the setting procedure for waveform output by a compare match.
Section 11 16-Bit Timer Pulse Unit (TPU) 2. Examples of waveform output operation Figure 11.6 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change. TCNT value H'FFFF TGRA TGRB Time H'0000 No change No change 1 output TIOCA TIOCB No change No change 0 output Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel’s counter input clock or compare match signal as the input capture source.
Section 11 16-Bit Timer Pulse Unit (TPU) 2. Example of input capture operation Figure 11.9 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Section 11 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation Setting Procedure: Figure 11.10 shows an example of the synchronous operation setting procedure.
Section 11 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation: Figure 11.11 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.28 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGRA_0 TGRC_0 TGRB_0 TGRD_0 TGRA_3 TGRC_3 TGRB_3 TGRD_3 3 • When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 11.12.
Section 11 16-Bit Timer Pulse Unit (TPU) Example of Buffer Operation Setting Procedure: Figure 11.14 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or output compare register by means of TIOR. Buffer operation [1] [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. Set buffer operation [2] [3] Set the CST bit in TSTR to 1 to start the count operation. Start count [3] Select TGR function Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation: 1. When TGR is an output compare register Figure 11.15 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
Section 11 16-Bit Timer Pulse Unit (TPU) 2. When TGR is an input capture register Figure 11.16 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 11.29 shows the register combinations used in cascaded operation.
Section 11 16-Bit Timer Pulse Unit (TPU) Examples of Cascaded Operation: Figure 11.18 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0–% to 100–% duty cycle. Designating TGR compare match as the counter clearing source enables the cycle to be set in that register. All channels can be designated for PWM mode independently.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure: Figure 11.20 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source.
Section 11 16-Bit Timer Pulse Unit (TPU) TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 Time TIOCA Figure 11.21 Example of PWM Mode Operation (1) Figure 11.22 shows an example of PWM mode 2 operation.
Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Section 11 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1. Phase counting mode 1 Figure 11.25 shows an example of phase counting mode 1 operation, and table 11.32 summarizes the TCNT up/down-count conditions.
Section 11 16-Bit Timer Pulse Unit (TPU) 2. Phase counting mode 2 Figure 11.26 shows an example of phase counting mode 2 operation, and table 11.33 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 11.26 Example of Phase Counting Mode 2 Operation Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 3. Phase counting mode 3 Figure 11.27 shows an example of phase counting mode 3 operation, and table 11.34 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 11.27 Example of Phase Counting Mode 3 Operation Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 4. Phase counting mode 4 Figure 11.28 shows an example of phase counting mode 4 operation, and table 11.35 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 11.28 Example of Phase Counting Mode 4 Operation Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Phase Counting Mode Application Example: Figure 11.29 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB.
Section 11 16-Bit Timer Pulse Unit (TPU) Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed cycle capture) TGRB_1 (position cycle capture) TCNT_0 TGRA_0 (speed control cycle) + - TGRC_0 (position control cycle) + - TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 11.29 Phase Counting Mode Application Example 11.5 Interrupt Sources There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
Section 11 16-Bit Timer Pulse Unit (TPU) In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. 11.9 Operation Timing 11.9.1 Input/Output Timing TCNT Count Timing: Figure 11.30 shows TCNT count timing in internal clock operation, and figure 11.31 shows TCNT count timing in external clock operation. φ Internal clock Rising edge Falling edge TCNT input clock TCNT N–1 N N+1 N+2 Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the (TIOC pin) TCNT input clock is generated. Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture: Figure 11.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 11.35 shows the timing when counter clearing by input capture occurrence is specified. φ Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 11.34 Counter Clear Timing (Compare Match) φ Input capture signal Counter clear signal TCNT N H'0000 N TGR Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing: Figures 11.36 and 11.37 show the timings in buffer operation. φ TCNT n n+1 Compare match signal TGRA, TGRB n TGRC, TGRD N N Figure 11.36 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT N TGRA, TGRB n TGRC, TGRD N+1 N N+1 n N Figure 11.37 Buffer Operation Timing (Input Capture) 11.9.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) φ TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 11.38 TGI Interrupt Timing (Compare Match) TGF Flag Setting Timing in Case of Input Capture: Figure 11.39 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing. φ Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 11.39 TGI Interrupt Timing (Input Capture) Rev.7.00 Mar.
Section 11 16-Bit Timer Pulse Unit (TPU) TCFV Flag/TCFU Flag Setting Timing: Figure 11.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing. Figure 11.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and the TCIU interrupt request signal timing. φ TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 11.42 shows the timing for status flag clearing by the CPU, and figure 11.43 shows the timing for status flag clearing by the DTC or DMAC. TSR write cycle T2 T1 φ TSR address Address Write signal Status flag Interrupt request signal Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.10 Usage Notes 11.10.1 Module Stop Mode Setting TPU operation can be disabled or enabled using the module stop control register. The initial setting is for TPU operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 24, Power-Down Modes. 11.10.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.3 Caution on Cycle Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: φ f= (N + 1) Where f: Counter frequency φ: Operating frequency N: TGR set value 11.10.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 11.46 shows the timing in this case. TCNT write cycle T2 T1 φ TCNT address Address Write signal TCNT input clock TCNT N M TCNT write data Figure 11.46 Contention between TCNT Write and Increment Operations Rev.7.00 Mar.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.6 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 11.47 shows the timing in this case. TGR write cycle T2 T1 φ TGR address Address Write signal Compare match signal Disabled TCNT N N+1 TGR N M TGR write data Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 11.48 shows the timing in this case. TGR write cycle T2 T1 φ Buffer register address Address Write signal Compare match signal Buffer register write data Buffer register TGR N M N Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.8 Contention between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 11.49 shows the timing in this case. TGR read cycle T2 T1 φ TGR address Address Read signal Input capture signal TGR X Internal data bus M M Figure 11.49 Contention between TGR Read and Input Capture Rev.7.00 Mar.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.9 Contention between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 11.50 shows the timing in this case. TGR write cycle T2 T1 φ Address TGR address Write signal Input capture signal TCNT TGR M M Figure 11.50 Contention between TGR Write and Input Capture Rev.7.00 Mar.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.10 Contention between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 11.51 shows the timing in this case. Buffer register write cycle T2 T1 φ Buffer register address Address Write signal Input capture signal TCNT TGR Buffer register N M N M Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.11 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 11.52 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. φ TCNT input clock TCNT H'FFFF H'0000 Counter clearing signal TGF Disabled TCFV Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.12 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, when overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 11.53 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T2 T1 φ TCNT address Address Write signal TCNT TCNT write data H'FFFF M TCFV flag Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.13 Multiplexing of I/O Pins In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. 11.10.
Section 11 16-Bit Timer Pulse Unit (TPU) Rev.7.00 Mar.
Section 12 Programmable Pulse Generator (PPG) Section 12 Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that can operate both simultaneously and independently. The block diagram of PPG is shown in figure 12.1. 12.
Section 12 Programmable Pulse Generator (PPG) Compare match signals Control logic PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 Legend: PMR PCR NDERH NDERL NDRH NDRL PODRH PODRL NDERH NDERL PMR PCR Pulse output pins, group 3 PODRH NDRH PODRL NDRL Pulse output pins, group 2 Pulse output pins, group 1 Pulse output pins, group 0 : PPG output mode register : PPG output control register : Next data enable register H : Next data enable register L : Next data register H : Next
Section 12 Programmable Pulse Generator (PPG) 12.2 Input/Output Pins Table 12.1 shows the PPG pin configuration. Table 12.1 Pin Configuration Pin Name I/O Function PO15 Output Group 3 pulse output PO14 Output PO13 Output PO12 Output PO11 Output PO10 Output PO9 Output PO8 Output PO7 Output PO6 Output PO5 Output PO4 Output PO3 Output PO2 Output PO1 Output PO0 Output 12.
Section 12 Programmable Pulse Generator (PPG) 12.3.1 Next Data Enable Registers H, L (NDERH, NDERL) NDERH, NDERL enable or disable pulse output on a bit-by-bit basis. For outputting pulse by the PPG, set the corresponding DDR to 1.
Section 12 Programmable Pulse Generator (PPG) 12.3.2 Output Data Registers H, L (PODRH, PODRL) PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified.
Section 12 Programmable Pulse Generator (PPG) NDRH If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Bit Bit Name Initial Value R/W Description 7 NDR15 0 R/W Next Data Register 15 to 8 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR.
Section 12 Programmable Pulse Generator (PPG) NDRL If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Bit Bit Name Initial Value R/W Description 7 NDR7 0 R/W Next Data Register 7 to 0 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR.
Section 12 Programmable Pulse Generator (PPG) 12.3.4 PPG Output Control Register (PCR) PCR selects output trigger signals on a group-by-group basis. For details on output trigger selection, refer to section 12.3.5, PPG Output Mode Register (PMR). Bit Bit Name Initial Value R/W Description 7 G3CMS1 1 R/W Group 3 Compare Match Select 1 and 0 6 G3CMS0 1 R/W Select output trigger of pulse output group 3.
Section 12 Programmable Pulse Generator (PPG) 12.3.5 PPG Output Mode Register (PMR) PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG updates its output values at compare match A or B of the TPU that becomes the output trigger. For details, refer to section 12.4.4, Non-Overlapping Pulse Output.
Section 12 Programmable Pulse Generator (PPG) Bit Bit Name Initial Value R/W Description 3 G3NOV 0 R/W Group 3 Non-Overlap Selects normal or non-overlapping operation for pulse output group 3. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) 2 G2NOV 0 R/W Group 2 Non-Overlap Selects normal or non-overlapping operation for pulse output group 2.
Section 12 Programmable Pulse Generator (PPG) 12.4 Operation Figure 12.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values.
Section 12 Programmable Pulse Generator (PPG) 12.4.1 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 12.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. φ N TCNT TGRA N+1 N Compare match A signal n NDRH PODRH PO8 to PO15 m n m n Figure 12.3 Timing of Transfer and Output of NDR Contents (Example) Rev.7.00 Mar.
Section 12 Programmable Pulse Generator (PPG) 12.4.2 Sample Setup Procedure for Normal Pulse Output Figure 12.4 shows a sample procedure for setting up normal pulse output. Normal PPG output Select TGR functions [1] Set TGRA value [2] Set counting operation [3] Select interrupt request [4] Set initial output data [5] Enable pulse output [6] Select output trigger [7] [1] Set TIOR to make TGRA an output compare register (with output disabled). [2] Set the PPG output trigger period.
Section 12 Programmable Pulse Generator (PPG) 12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) Figure 12.5 shows an example in which pulse output is used for cyclic five-phase pulse output. TCNT value Compare match TCNT TGRA H'0000 Time 80 NDRH PODRH 00 C0 80 40 C0 60 40 20 60 30 20 10 30 18 10 08 18 88 08 80 88 C0 80 40 C0 PO15 PO14 PO13 PO12 PO11 Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output) 1.
Section 12 Programmable Pulse Generator (PPG) 12.4.4 Non-Overlapping Pulse Output During non-overlapping operation, transfer from NDR to PODR is performed as follows: • NDR bits are always transferred to PODR bits at compare match A. • At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 12.6 illustrates the non-overlapping pulse output operation.
Section 12 Programmable Pulse Generator (PPG) Compare match A Compare match B Write to NDR Write to NDR NDR PODR 0 output 0/1 output Write to NDR Do not write here to NDR here 0 output 0/1 output Do not write to NDR here Write to NDR here Figure 12.7 Non-Overlapping Operation and NDR Write Timing Rev.7.00 Mar.
Section 12 Programmable Pulse Generator (PPG) 12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output Figure 12.8 shows a sample procedure for setting up non-overlapping pulse output.
Section 12 Programmable Pulse Generator (PPG) 12.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) Figure 12.9 shows an example in which pulse output is used for four-phase complementary nonoverlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 NDRH PODRH Time 95 00 65 95 59 05 65 56 41 59 95 50 56 65 14 95 05 65 Non-overlap margin PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 12.
Section 12 Programmable Pulse Generator (PPG) 1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. 2.
Section 12 Programmable Pulse Generator (PPG) 12.4.7 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 12.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 12.9. TCNT value TGRB TCNT TGRA H'0000 NDRH PODRL Time 95 00 65 95 59 05 65 56 41 59 95 50 56 65 14 95 05 PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 12.
Section 12 Programmable Pulse Generator (PPG) 12.4.8 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 12.11 shows the timing of this output. φ TIOC pin Input capture signal NDR N PODR M PO M N N Figure 12.11 Pulse Output Triggered by Input Capture (Example) 12.
Section 12 Programmable Pulse Generator (PPG) Rev.7.00 Mar.
Section 13 8-Bit Timers (TMR) Section 13 8-Bit Timers (TMR) This LSI has an on-chip 8-bit timer module with two channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used to count external events and be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. 13.
Section 13 8-Bit Timers (TMR) Figure 13.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1).
Section 13 8-Bit Timers (TMR) 13.2 Input/Output Pins Table 13.1 shows the pin configuration of the 8-bit timer module. Table 13.
Section 13 8-Bit Timers (TMR) 13.3.1 Timer Counter (TCNT) TCNT is 8-bit up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR are used to select a clock. TCNT can be cleared by an external reset input or by a compare match signal A or B. Which signal is to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When TCNT overflows from H'FF to H'00, OVF in TCSR is set to 1.
Section 13 8-Bit Timers (TMR) 13.3.4 Timer Control Register (TCR) TCR selects the clock source and the time at which TCNT is cleared, and controls interrupts. Bit Bit Name Initial Value R/W 7 CMIEB 0 R/W Description Compare Match Interrupt Enable B Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1.
Section 13 8-Bit Timers (TMR) Table 13.
Section 13 8-Bit Timers (TMR) 13.3.5 Timer Control/Status Register (TCSR) TCSR displays status flags, and controls compare match output.
Section 13 8-Bit Timers (TMR) Bit Bit Name Initial Value R/W Description 3 2 OS3 OS2 0 0 R/W R/W Output Select 3 and 2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs.
Section 13 8-Bit Timers (TMR) TCSR_1 Bit 7 Bit Name CMFB Initial Value R/W Description 0 R/(W)* Compare Match Flag B [Setting condition] • Set when TCNT matches TCORB [Clearing conditions] 6 CMFA 0 R/(W)* • Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB • When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 Compare Match Flag A [Setting condition] • Set when TCNT matches TCORA [Clearing conditions] 5 OVF 0 R/(W)* • Cleared by reading CMFA when
Section 13 8-Bit Timers (TMR) Bit Bit Name Initial Value R/W Description 3 2 OS3 OS2 0 0 R/W R/W Output Select 3 and 2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs.
Section 13 8-Bit Timers (TMR) 13.4 Operation 13.4.1 Pulse Output Figure 13.2 shows an example that the 8-bit timer is used to generate a pulse output with a selected duty cycle. The control bits are set as follows: [1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is cleared at a TCORA compare match. [2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match.
Section 13 8-Bit Timers (TMR) 13.5 Operation Timing 13.5.1 TCNT Incrementation Timing Figure 13.3 shows the count timing for internal clock input. Figure 13.4 shows the count timing for external clock signal. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values.
Section 13 8-Bit Timers (TMR) 13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare match signal is not generated until the next incrementation clock input. Figure 13.5 shows this timing.
Section 13 8-Bit Timers (TMR) 13.5.3 Timing of Timer Output when Compare-Match Occurs When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in TCSR. Figure 13.6 shows the timing when the output is set to toggle at compare match A. φ Compare match A signal Timer output pin Figure 13.6 Timing of Timer Output 13.5.4 Timing of Compare Match Clear TCNT is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 13.
Section 13 8-Bit Timers (TMR) 13.5.5 Timing of TCNT External Reset TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 13.8 shows the timing of this operation. φ External reset input pin Clear signal TCNT N–1 N H'00 Figure 13.8 Timing of Clearance by External Reset 13.5.
Section 13 8-Bit Timers (TMR) 13.6 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match count mode). In this case, the timer operates as below. 13.6.
Section 13 8-Bit Timers (TMR) 13.7 Interrupt Sources 13.7.1 Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 13.3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 13.
Section 13 8-Bit Timers (TMR) 13.8 Usage Notes 13.8.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 13.10 shows this operation. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 13.10 Contention between TCNT Write and Clear Rev.7.00 Mar.
Section 13 8-Bit Timers (TMR) 13.8.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 13.11 shows this operation. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 13.11 Contention between TCNT Write and Increment Rev.7.00 Mar.
Section 13 8-Bit Timers (TMR) 13.8.3 Contention between TCOR Write and Compare Match During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is inhibited even if a compare match event occurs as shown in figure 13.12. When using the TMR, ICR input capture is in contention with compare match in the same way as writes to the TCOR. In such cases input capture has precedence and the compare match signal is inhibited.
Section 13 8-Bit Timers (TMR) 13.8.4 Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 13.4. Table 13.4 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change 13.8.
Section 13 8-Bit Timers (TMR) Table 13.5 Switching of Internal Clock and TCNT Operation No.
Section 13 8-Bit Timers (TMR) No. 4 Timing of Switchover by Means of CKS1 TCNT Clock Operation and CKS0 Bits Switching from high to high Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit write Notes: 1. 2. 3. 4. 13.8.6 Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented.
Section 13 8-Bit Timers (TMR) Rev.7.00 Mar.
Section 14 Watchdog Timer (WDT) Section 14 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At the same time, the WDT can also generate an internal reset signal. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows.
Section 14 Watchdog Timer (WDT) Clock WDTOVF Internal reset signal* Clock select Reset control RSTCSR TCNT φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock sources TSCR Module bus Bus interface Internal bus Overflow Interrupt control WOVI (interrupt request signal) WDT Legend: : Timer control/status register TCSR : Timer counter TCNT RSTCSR : Reset control/status register Note: * An internal reset signal can be generated by the register setting. Figure 14.
Section 14 Watchdog Timer (WDT) 14.3 Register Descriptions The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, refer to section 14.6.1, Notes on Register Access. • Timer counter (TCNT) • Timer control/status register (TCSR) • Reset control/status register (RSTCSR) 14.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter.
Section 14 Watchdog Timer (WDT) Bit Bit Name Initial Value R/W Description 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode When TCNT overflows, an interval timer interrupt (WOVI) is requested. 1: Watchdog timer mode When TCNT overflows, the WDTOVF signal is output. 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00.
Section 14 Watchdog Timer (WDT) 14.3.3 Reset Control/Status Register (RSTCSR) RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows. Bit 7 Bit Name WOVF Initial Value R/W Description 0 R/(W)* Watchdog Timer Overflow Flag This bit is set when TCNT overflows in watchdog timer mode.
Section 14 Watchdog Timer (WDT) 14.4 Operation 14.4.1 Watchdog Timer Mode To use the WDT as a watchdog timer mode, set the WT/IT and TME bits in TCSR to 1. If TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal is output. This ensures that TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflow occurs.
Section 14 Watchdog Timer (WDT) TCNT count Overflow H'FF Time H'00 WT/IT=1 TME=1 H'00 written to TCNT WOVF=1 WDTOVF and internal reset are generated WT/IT=1 TME=1 H'00 written to TCNT WDTOVF signal 132 states*2 Internal reset signal*1 518 states Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated. 2. 130 states when the RSTE bit is cleared to 0. Figure 14.2 Operation in Watchdog Timer Mode 14.4.
Section 14 Watchdog Timer (WDT) TCNT count Overflow H'FF Overflow Overflow Overflow Time H'00 WOVI WT/IT=0 TME=1 WOVI WOVI WOVI Legend: WOVI: Interval timer interrupt request generation Figure 14.3 Operation in Interval Timer Mode 14.5 Interrupt Source During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine.
Section 14 Watchdog Timer (WDT) TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition shown in figure 14.4 to write to TCNT or TCSR. The transfer instruction writes the lower byte data to TCNT or TCSR according to the satisfied condition. To write to RSTCSR, execute a word transfer instruction for address H'FFBE. A byte transfer instruction cannot perform writing to RSTCSR. The method of writing 0 to the WOVF bit differs from that of writing to the RSTE bit.
Section 14 Watchdog Timer (WDT) 14.6.2 Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the next cycle after the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 14.5 shows this operation. TCNT write cycle T1 T2 Next cycle φ Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 14.5 Contention between TCNT Write and Increment 14.6.
Section 14 Watchdog Timer (WDT) 14.6.5 Internal Reset in Watchdog Timer Mode This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer mode operation, but TCNT and TCSR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore, read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag. 14.6.
Section 14 Watchdog Timer (WDT) Rev.7.00 Mar.
Section 15 Serial Communication Interface (SCI, IrDA) Section 15 Serial Communication Interface (SCI, IrDA) This LSI has five independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
Section 15 Serial Communication Interface (SCI, IrDA) • Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error • Average transfer rate generator (only for H8S/2378R Group): The following transfer rate can be selected (SCI_2 only) 115.152 or 460.606 kbps at 10.667-MHz operation 115.196, 460.
Bus interface Section 15 Serial Communication Interface (SCI, IrDA) Module data bus RDR RxD RSR SCMR SSR SCR SMR SEMR TDR TSR BRR φ Baud rate generator Transmission/ reception control TxD Parity generation φ/4 φ/16 φ/64 Clock Parity check External clock SCK Legend: RSR RDR TSR TDR SMR SCR SSR SCMR BRR SEMR Internal data bus TEI TXI RXI ERI : Receive shift register : Receive data register : Transmit shift register : Transmit data register : Serial mode register : Serial control register :
Section 15 Serial Communication Interface (SCI, IrDA) 15.2 Input/Output Pins Table 15.1 shows the pin configuration of the serial communication interface. Table 15.
Section 15 Serial Communication Interface (SCI, IrDA) 15.3 Register Descriptions The SCI has the following registers. The serial mode register (SMR), serial status register (SSR), and serial control register (SCR) are described separately for normal serial communication interface mode and Smart Card interface mode because their bit functions partially differ.
Section 15 Serial Communication Interface (SCI, IrDA) • Transmit shift register_3 (TSR_3) • Receive data register_3 (RDR_3) • Transmit data register_3 (TDR_3) • Serial mode register_3 (SMR_3) • Serial control register_3 (SCR_3) • Serial status register_3 (SSR_3) • Smart card mode register_3 (SCMR_3) • Bit rate register_3 (BRR_3) • Receive shift register_4 (RSR_4) • Transmit shift register_4 (TSR_4) • Receive data register_4 (RDR_4) • Transmit data register_4 (TDR_4) • Serial mode register_4 (SMR_4) • Seria
Section 15 Serial Communication Interface (SCI, IrDA) already been written to TDR during serial transmission, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. 15.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data.
Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting.
Section 15 Serial Communication Interface (SCI, IrDA) Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 GM 0 R/W GSM Mode When this bit is set to 1, the SCI operates in GSM mode. In GSM mode, the timing of the TEND setting is advanced by 11.0 etu (Elementary time unit: the time for transfer of 1 bit), and clock output control mode addition is performed. For details, refer to section 15.7.8, Clock Output Control.
Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 1 CKS1 0 R/W Clock Select 1 and 0: 0 CKS0 0 R/W These bits select the clock source for the on-chip baud rate generator. 00: φ clock (n = 0) 01: φ/4 clock (n = 1) 10: φ/16 clock (n = 2) 11: φ/64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 15.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 15.3.
Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 5 TE 0 R/W Transmit Enable When this bit s set to 1, transmission is enabled. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. The TDRE flag in SSR is fixed at 1 if transmission is disabled by clearing this bit to 0.
Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, TEI interrupt request is enabled. TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0. 1 CKE1 0 R/W Clock Enable 1 and 0 0 CKE0 0 R/W Selects the clock source and SCK pin function.
Section 15 Serial Communication Interface (SCI, IrDA) Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled.
Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 TEIE 0 R/W Transmit End Interrupt Enable Write 0 to this bit in Smart Card interface mode. 1 CKE1 0 R/W Clock Enable 1 and 0 0 CKE0 0 R/W Enables or disables clock output from the SCK pin. The clock output can be dynamically switched in GSM mode. For details, refer to section 15.7.8, Clock Output Control.
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit functions of SSR differ in normal serial communication interface mode and Smart Card interface mode.
Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 5 ORER 0 R/(W)* Overrun Error Indicates that an overrun error occurred while receiving and the reception has ended abnormally. [Setting condition] • When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1.
Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 3 PER 0 R/(W)* Parity Error Indicates that a parity error occurred while receiving in asynchronous mode and the reception has ended abnormally. [Setting condition] • When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1.
Section 15 Serial Communication Interface (SCI, IrDA) Smart Card Interface Mode (When SMIF in SCMR is 1) Bit 7 Bit Name TDRE Initial Value 1 R/W Description 1 R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR, and data writing to TDR is enabled.
Section 15 Serial Communication Interface (SCI, IrDA) Bit 5 Bit Name ORER Initial Value 0 R/W Description 1 R/(W)* Overrun Error Indicates that an overrun error occurred while receiving and the reception has ended abnormally. [Setting condition] When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1.
Section 15 Serial Communication Interface (SCI, IrDA) Bit 3 Bit Name PER Initial Value 0 R/W Description 1 R/(W)* Parity Error Indicates that a parity error occurred while receiving in asynchronous mode and the reception has ended abnormally. [Setting condition] • When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1.
Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 TEND 1 R Transmit End This bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to TDR.
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.8 Smart Card Mode Register (SCMR) SCMR selects Smart Card interface mode and its format. Bit Bit Name Initial Value R/W 7 to 4 ⎯ All 1 ⎯ 3 SDIR Description Reserved These bits are always read as 1. 0 R/W Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: LSB-first in transfer 1: MSB-first in transfer The bit setting is valid only when the transfer data format is 8 bits.
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 15.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and Smart Card interface mode.
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency φ (MHz) 8 9.8304 10 12 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 141 0.03 2 174 –0.26 2 177 –0.25 2 212 0.03 150 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16 300 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 600 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.
Section 15 Serial Communication Interface (SCI, IrDA) Operating Frequency φ (MHz) 17.2032 18 19.6608 20 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 75 0.48 3 79 –0.12 3 86 0.31 3 88 –0.25 150 2 223 0.00 2 233 0.16 2 255 0.00 3 64 0.16 300 2 111 0.00 2 116 0.16 2 127 0.00 2 129 0.16 600 1 223 0.00 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 111 0.00 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 223 0.
Section 15 Serial Communication Interface (SCI, IrDA) Operating Frequency φ (MHz) 2 35* Bit Rate (bit/s) n N Error (%) 110 3 154 0.23 150 3 113 –0.06 300 2 227 –0.06 600 2 113 –0.06 1200 1 227 –0.06 2400 1 113 –0.06 4800 0 227 –0.06 9600 0 113 –0.06 19200 0 56 –0.06 31250 0 34 0.00 38400 0 27 1.73 Notes: 1. Supported on the H8S/2378 0.18μm F-ZTAT Group and H8S/2378R 0.18μm F-ZTAT Group only. 2. Supported on the H8S/2378 only. Rev.7.00 Mar.
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bit/s) n N 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 19.6608 614400 0 0 20 625000 0 0 25 781250 0 0 30 937500 0 0 33 1031250 0 0 1 1062500 0 0 *2 1093750 0 0 34* 35 Notes: 1.
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 19.6608 4.9152 307200 20 5.0000 312500 25 6.2500 390625 30 7.5000 468750 33 8.
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) Bit Rate (bit/s) n 8 10 16 N n N n N 20 n N 25 n N 30 n N 3 233 1 2 34* 33 35* n N n N n N 110 250 3 124 ⎯ ⎯ 3 249 500 2 249 ⎯ ⎯ 3 124 ⎯ ⎯ 1k 2 124 ⎯ ⎯ 2 249 ⎯ ⎯ 3 97 3 116 3 128 3 132 3 136 2.
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 8 1.3333 1333333.3 20 3.3333 3333333.3 10 1.6667 1666666.7 25 4.1667 4166666.7 12 2.0000 2000000.0 30 5.0000 5000000.0 14 2.3333 2333333.3 33 5.5000 5500000.0 5.6667 5666666.7 2 5.8336 5833625.0 16 2.6667 2666666.
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372) φ (MHz) Maximum Bit Rate (bit/s) n N φ (MHz) Maximum Bit Rate (bit/s) n N 10.00 13441 0 0 20.00 26882 0 0 10.7136 14400 0 0 25.00 33602 0 0 13.00 17473 0 0 30.00 40323 0 0 14.2848 19200 0 0 33.00 44355 0 0 0 1 34.00* 45699 0 0 0 2 35.00* 47043 0 0 16.00 18.00 21505 24194 0 0 Notes: 1.
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.10 IrDA Control Register (IrCR) IrCR selects the function of SCI_0. Bit Bit Name Initial Value R/W Description 7 IrE 0 R/W IrDA Enable Specifies normal SCI mode or IrDA mode for SCI_0 input/output.
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.11 Serial Extension Mode Register (SEMR) SEMR selects the clock source in asynchronous mode. The basic clock can be automatically set by selecting the average transfer rate. Bit Bit Name Initial Value R/W Description 7 to 4 ⎯ Undefined ⎯ Reserved 3 ABCS If these bits are read, an undefined value will be returned and cannot be modified.
Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 1 0 ACS2 ACS1 ACS0 0 0 0 R/W R/W R/W Asynchronous clock source selection (valid when CKE1 = 1 in asynchronous mode) Selects the clock source for the average transfer rate. The basic clock can be automatically set by selecting the average transfer rate in spite of the value of ABCS. 000: External clock input 001: Selects 115.152 kbps which is the average transfer rate dedicated for φ= 10.667 MHz.
Section 15 Serial Communication Interface (SCI, IrDA) 15.4 Operation in Asynchronous Mode Figure 15.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transfer data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level).
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.
Section 15 Serial Communication Interface (SCI, IrDA) 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched at the middle of each bit by sampling the data at the rising edge of the 8th pulse of the basic clock as shown in figure 15.3.
Section 15 Serial Communication Interface (SCI, IrDA) 15.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin.
Section 15 Serial Communication Interface (SCI, IrDA) 15.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 15.5. Do not write to SMR, SCMR, IrCR, or SEMR while the SCI is operating. This also applies to writing the same data as the current register contents. When the operating mode, transfer format, etc.
Section 15 Serial Communication Interface (SCI, IrDA) 15.4.5 Data Transmission (Asynchronous Mode) Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Section 15 Serial Communication Interface (SCI, IrDA) [1] Initialization Start of transmission Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 15 Serial Communication Interface (SCI, IrDA) 15.4.6 Serial Data Reception (Asynchronous Mode) Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.9 shows a sample flowchart for serial data reception. Table 15.
Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] Start of reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error handling and break detection: Read ORER, PER, and If a receive error occurs, read the [2] FER flags in SSR ORER, PER, and FER flags in SSR to identify the error.
Section 15 Serial Communication Interface (SCI, IrDA) [3] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 No PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SSR to 0 Figure 15.9 Sample Serial Reception Data Flowchart (2) Rev.7.00 Mar.
Section 15 Serial Communication Interface (SCI, IrDA) 15.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code.
Section 15 Serial Communication Interface (SCI, IrDA) Transmitting station Serial communication line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'AA H'01 (MPB= 1) ID transmission cycle = receiving station specification (MPB= 0) Data transmission cycle = data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 15.
Section 15 Serial Communication Interface (SCI, IrDA) [1] [1] SCI initialization: Initialization Start of transmission Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND = 1? Yes No Break output? The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled.
Section 15 Serial Communication Interface (SCI, IrDA) 15.5.2 Multiprocessor Serial Data Reception Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 15.
Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [2] ID reception cycle: Set the MPIE bit in SCR to 1. Start of reception Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR FER ∨ ORER = 1? [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID.
Section 15 Serial Communication Interface (SCI, IrDA) [5] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev.7.00 Mar.
Section 15 Serial Communication Interface (SCI, IrDA) 15.6 Operation in Clocked Synchronous Mode Figure 15.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character of communication data consists of 8-bit data. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next.
Section 15 Serial Communication Interface (SCI, IrDA) 15.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 15.15. Do not write to SMR, SCMR, IrCR, or SEMR while the SCI is operating. This also applies to writing the same data as the current register contents. When the operating mode, transfer format, etc.
Section 15 Serial Communication Interface (SCI, IrDA) 1. The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated.
Section 15 Serial Communication Interface (SCI, IrDA) [1] Initialization Start of transmission Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? [3] Yes Read TEND flag in SSR [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin.
Section 15 Serial Communication Interface (SCI, IrDA) 15.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the received data in RSR. 2.
Section 15 Serial Communication Interface (SCI, IrDA) [1] Initialization Start of reception [2] Read ORER flag in SSR Yes [3] ORER = 1? No Error processing (Continued below) Read RDRF flag in SSR [4] No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [5] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
Section 15 Serial Communication Interface (SCI, IrDA) 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations after the SCI is initialized.
Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] SCI initialization: [1] The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Start of transmission/reception Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 15 Serial Communication Interface (SCI, IrDA) 15.7 Operation in Smart Card Interface Mode The SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 15.7.1 Pin Connection Example Figure 15.21 shows an example of connection with the Smart Card.
Section 15 Serial Communication Interface (SCI, IrDA) 15.7.2 Data Format (Except for Block Transfer Mode) Figure 15.22 shows the transfer data format in Smart Card interface mode. • One frame consists of 8-bit data plus a parity bit in asynchronous mode. • In transmission, a guard time of at least 2 etu (Elementary time unit: time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame.
Section 15 Serial Communication Interface (SCI, IrDA) As in the above sample start character, with the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV bits in SCMR to 0. According to the Smart Card regulations, clear the O/E bit in SMR to 0 to select even parity mode.
Section 15 Serial Communication Interface (SCI, IrDA) falling edge of the start bit using the basic clock, and performs internal synchronization. As shown in figure 15.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is given by the following formula. M = ⏐ (0.5 – ⏐D – 0.5⏐ 1 ) – (L – 0.
Section 15 Serial Communication Interface (SCI, IrDA) 15.7.5 Initialization Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Clear the error flags ERS, PER, and ORER in SSR to 0. 3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR. Set the PE bit to 1. 4. Set the SMIF, SDIR, and SINV bits in SCMR.
Section 15 Serial Communication Interface (SCI, IrDA) 15.7.6 Data Transmission (Except for Block Transfer Mode) As data transmission in Smart Card interface mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). Figure 15.26 illustrates the retransfer operation when the SCI is in transmit mode. 1.
Section 15 Serial Communication Interface (SCI, IrDA) nth transfer frame Transfer frame n+1 Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 TDRE Transfer to TSR from TDR Transfer to TSR from TDR Transfer to TSR from TDR TEND [7] [9] FER/ERS [6] [8] Figure 15.26 Retransfer Operation in SCI Transmit Mode The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag generation timing is shown in figure 15.
Section 15 Serial Communication Interface (SCI, IrDA) Start Initialization Start transmission ERS = 0? No Yes Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted ? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 15.28 Example of Transmission Processing Flow 15.7.
Section 15 Serial Communication Interface (SCI, IrDA) 1. If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is generated. The PER bit in SSR should be cleared to 0 before the next parity bit is sampled. 2. The RDRF bit in SSR is not set for a frame in which an error has occurred. 3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1. 4.
Section 15 Serial Communication Interface (SCI, IrDA) Start Initialization Start reception ORER = 0 and PER = 0 No Yes Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 15.30 Example of Reception Processing Flow 15.7.8 Clock Output Control When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width.
Section 15 Serial Communication Interface (SCI, IrDA) When turning on the power or switching between Smart Card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty cycle. Powering On: To secure the clock duty cycle from power-on, the following switching procedure should be followed. 1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. 2.
Section 15 Serial Communication Interface (SCI, IrDA) 15.8 IrDA Operation When the IrDA function is enabled with bit IrE in IrCR, the SCI_0 TxD0 and RxD0 signals are subjected to waveform encoding/decoding conforming to IrDA specification version 1.0 (IrTxD and IrRxD pins). By connecting these pins to an infrared transceiver/receiver, it is possible to implement infrared transmission/reception conforming to the IrDA specification version 1.0 system. In the IrDA specification version 1.
Section 15 Serial Communication Interface (SCI, IrDA) In the specification, the high pulse width is fixed at a minimum of 1.41 µs, and a maximum of (3/16 + 2.5%) × bit rate or (3/16 × bit rate) + 1.08 µs. When system clock φ is 20 MHz, 1.6 µs can be set for a high pulse width with a minimum value of 1.41 µs. When the serial data is 1, no pulse is output.
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.12 Settings of Bits IrCKS2 to IrCKS0 Bit Rate (bps) (Above)/Bit Period × 3/16 (µs) (Below) Operating Frequency φ (MHz) 2400 9600 19200 38400 57600 115200 78.13 19.53 9.77 4.88 3.26 1.63 8 100 100 100 100 100 100 9.8304 100 100 100 100 100 100 10 100 100 100 100 100 100 12 101 101 101 101 101 101 12.288 101 101 101 101 101 101 14 101 101 101 101 101 101 14.
Section 15 Serial Communication Interface (SCI, IrDA) 15.9 Interrupt Sources 15.9.1 Interrupts in Normal Serial Communication Interface Mode Table 15.13 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated.
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.
Section 15 Serial Communication Interface (SCI, IrDA) 15.9.2 Interrupts in Smart Card Interface Mode Table 15.14 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt (TEI) request cannot be used in this mode. Table 15.
Section 15 Serial Communication Interface (SCI, IrDA) When performing transfer using the DTC or DMAC, it is essential to set and enable the DTC or DMAC before carrying out SCI setting. For details on the DTC or DMAC setting procedures, refer to section 9, Data Transfer Controller (DTC) or section 7, DMA Controller (DMAC). In receive operations, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1.
Section 15 Serial Communication Interface (SCI, IrDA) 15.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. 15.10.
Section 15 Serial Communication Interface (SCI, IrDA) 15.10.7 Operation in Case of Mode Transition • Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode or software standby mode transition. TSR, TDR, and SSR are reset. The output pin states in module stop mode or software standby mode depend on the port settings, and become high-level output after the relevant mode is cleared.
Section 15 Serial Communication Interface (SCI, IrDA) Figure 15.39 shows a sample flowchart for mode transition during reception. All data transmitted? No [1] Yes Read TEND flag in SSR TEND = 1 No Yes TE = 0 [2] Transition to software standby mode [3] [1] Data being transmitted is interrupted.
Section 15 Serial Communication Interface (SCI, IrDA) End of transmission Start of transmission Transition to software standby Exit from software standby TE bit Port input/output SCK output pin TxD output pin Port input/output High output Port Start Stop Port input/output Port SCI TxD output High output SCI TxD output Figure 15.
Section 15 Serial Communication Interface (SCI, IrDA) Read RDRF flag in SSR RDRF = 1 No [1] [1] Receive data being received becomes invalid. [2] [2] Includes module stop mode. Yes Read receive data in RDR RE = 0 Transition to software standby mode Exit from software standby mode Change operating mode? No Yes Initialization RE = 1 Figure 15.39 Sample Flowchart for Mode Transition during Reception Rev.7.00 Mar.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) Section 16 I2C Bus Interface 2 (IIC2) (Option) An I2C bus interface is an option. When using the optional functions, take notice of the following item: 1. For the masked ROM version, W is added to the model name of the product that uses optional functions. For example: HD6432375WFQ This LSI has a two-channel I2C bus interface. The I2C bus interface conforms to and provides a subset of the NXP Semiconductors I2C bus (inter-IC bus) interface (Rev.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) Transfer clock generation circuit SCL Transmission/ reception control circuit Output control ICCRA ICCRB ICMR Internal data bus Noise canceler ICDRT SDA Output control ICDRS SAR Address comparator Noise canceler ICDRR Bus state decision circuit Arbitration decision circuit ICSR ICEIR Interrupt generator Legend: ICCRA ICCRB ICMR ICSR ICIER ICDRT ICDRR ICDRS SAR : : : : : : : : : 2 I C bus control register A I2C bus control register B I2C mo
2 Section 16 I C Bus Interface 2 (IIC2) (Option) Vcc SCL in Vcc SCL SCL SDA SDA SCL out SDA in SCL in SCL SDA (Master) SCL SDA SDA out SCL in SCL out SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Figure 16.2 External Circuit Connections of I/O Pins 16.2 Input/Output Pins Table 16.1 shows the pin configuration of the I2C bus interface 2. Table 16.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) 16.3 Register Descriptions The I2C bus interface has the following registers.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) 16.3.1 I2C Bus Control Register A (ICCRA) ICCRA is an 8-bit readable/writable register that enables or disables the I2C bus interface, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. Bit Bit Name Initial Value R/W Description 7 ICE 0 R/W I C Bus Interface Enable 2 0: This module is halted. 1: This bit is enabled for transfer operations.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) Table 16.2 Transfer Rate Bit 3 Bit 2 Bit 1 Transfer Rate Bit 0 φ= CKS3 CKS2 CKS1 CKS0 Clock 8 MHz 4 0* 4 0* 0 1 1 0 0 1 φ= 20 MHz φ= 25 MHz 357 kHz 714 kHz* φ= 33 MHz φ= 1 34 MHz* 0 φ/28 1 φ/40 0 φ/48 167 kHz 208 kHz 417 kHz* 521 kHz* 688 kHz* 1 φ/64 125 kHz 156 kHz 313 kHz 391 kHz 0 φ/168 47.6 kHz 59.5 kHz 119 kHz 1 φ/100 80.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) I2C Bus Control Register B (ICCRB) 16.3.2 ICCRB is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in I2C control. Bit Bit Name Initial Value R/W Description 7 BBSY 0 R/W Bus Busy 2 This bit enables to confirm whether the I C bus is occupied or released and to issue start and stop conditions in master mode.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) Bit Bit Name Initial Value R/W Description 1 IICRST 0 R/W IIC control part reset 2 This bit resets control parts except for I C registers. If this bit is set to 1 when hang-up is occurred 2 because of communication failure during I C 2 operation, I C control part can be reset without setting ports and initializing registers. 0 ⎯ 1 ⎯ Reserved This bit is always read as 1. I2C Bus Mode Register (ICMR) 16.3.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) Bit Bit Name Initial Value R/W Description 2 BC2 0 R/W Bit Counter 2 to 0 1 BC1 0 R/W 0 BC0 0 R/W These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits is indicated. The data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) 16.3.4 I2C Bus Interrupt Enable Register (ICIER) ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received. Bit Bit Name Initial Value R/W 7 TIE 0 R/W Description Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI).
2 Section 16 I C Bus Interface 2 (IIC2) (Option) Bit Bit Name Initial Value R/W Description 4 NAKIE 0 R/W NACK receive interrupt enable This bit enables or disables the NACK receive interrupt request (NAKI) when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the NACKF, AL, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled. 1: NACK receive interrupt request (NAKI) is enabled.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) 16.3.5 I2C Bus Status Register (ICSR) ICSR is an 8-bit readable/writable register that performs confirmation of interrupt request flags and status.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) Bit Bit Name Initial Value R/W Description 4 NACKF 0 R/W No acknowledge detection flag [Setting condition] • When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 [Clearing condition] • 3 STOP 0 R/W When 0 is written in NACKF after reading NACKF =1 Stop condition detection flag [Setting condition] • In master mode, when a stop condition is detected after frame transfer • In slave mode, whe
2 Section 16 I C Bus Interface 2 (IIC2) (Option) Bit Bit Name Initial Value R/W Description 1 AAS 0 R/W Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting condition] • When the slave address is detected in slave receive mode • When the general call address is detected in slave receive mode.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) 16.3.7 I2C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the I2C bus shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible. The initial value of ICDRT is H'FF. 16.3.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) 16.4 Operation 16.4.1 I2C Bus Format Figure 16.3 shows the I2C bus formats. Figure 16.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) Legend: S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receiving device drives SDA to low. DATA: Transferred data P: 16.4.2 Stop condition. The master device drives SDA from low to high while SCL is high.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) SCL (master output) 1 2 3 4 5 6 SDA (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 7 8 Bit 1 Slave address 9 1 Bit 0 Bit 7 2 Bit 6 R/W SDA (slave output) A TDRE TEND Address + R/W ICDRT ICDRS User processing Data 1 Address + R/W [2] Instruction of start condition issuance Data 2 Data 1 [4] Write data to ICDRT (second byte). Clear TDRE and TEND. [5] Write data to ICDRT (third byte). Clear TDRE.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) 16.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCRA to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0. 2.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) Master transmit mode SCL (master output) Master receive mode 9 1 2 3 4 5 6 7 8 9 SDA (master output) SDA (slave output) 1 A A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS RDRF ICDRS Data 1 ICDRR User processing Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) Figure 16.7 Master Receive Mode Operation Timing 1 Rev.7.00 Mar.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) SCL (master output) 9 SDA (master output) A SDA (slave output) 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDRF RCVD ICDRS Data n Data n-1 ICDRR Data n Data n-1 User processing [5] Read ICDRR and clear RDRF after setting RCVD. [7] Read ICDRR, clear RDRF, and clear RCVD [6] Issue stop condition [8] Set slave receive mode Figure 16.8 Master Receive Mode Operation Timing 2 16.4.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) Slave receive mode SCL (master output) Slave transmit mode 9 1 2 3 4 5 6 7 8 SDA (master output) 9 1 A SCL (slave output) SDA (slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS ICDRT ICDRS Data 1 Data 2 Data 1 Data 3 Data 2 ICDRR User processing [2] Write data to ICDRT (data 1), and clear TDRE. [2] Write data to ICDRT (data 2), and clear TDRE.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) Slave receive mode Slave transmit mode SCL (master output) 9 SDA (master output) A 1 2 3 4 5 6 7 8 9 A/A SCL (slave output) SDA (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDRE TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) after clearing TRS [5] Clear TDRE Figure 16.10 Slave Transmit Mode Operation Timing 2 Rev.7.00 Mar.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) 16.4.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCRA to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCRA to 1.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) SCL (master output) 9 SDA (master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 1 Bit 7 SCL (slave output) SDA (slave output) A A RDRF ICDRS Data 1 Data 2 ICDRR User processing Data 1 [2] Read ICDRR, and clear RDRF. [2] Read ICDRR (dummy read), and clear RDRF. Figure 16.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) 16.4.6 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 16.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) Start Initialize Read BBSY in ICCRB [1] Test the status of the SCL and SDA lines.* [2] Select master transmit mode.* [3] Start condition issuance.* [4] Select transmit data for the first byte (slave address + R/W), and clear TDRE to 0. [5] Wait for 1 byte to be transmitted. [6] Test the acknowledge bit, transferred from the specified slave device.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE.* [2] Set acknowledge to the transmitting device.* [3] Dummy read ICDDR.* [4] Wait for 1 byte to be received. [5] Check if (last receive - 1). [6] Read the receive data, and clear RDRF to 0. [7] Set acknowledge of the final byte. Disable continuous receive (RCVD = 1). [8] Read receive data of (final byte - 1), and clear RDRF to 0.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) [1] Clear the flag AAS. Slave transmit mode Clear AAS in ICSR [1] [2] Set transmit data for ICDRT (except for the last data), and clear TDRE to 0. Write transmit data in ICDRT [2] [3] Wait for ICDRT empty. [4] Set the last byte of the transmit data, and clear TDRE to 0. Read TDRE in ICSR No [3] TDRE=1 ? [5] Wait the transmission end of the last byte. [6] Clear the flag TEND. Yes No [7] Set slave receive mode.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) Slave receive mode [1] Clear the flag AAS. Clear AAS in ICSR [1] Set ACKBT=0 in ICIER [2] [2] Set the acknowledge for the transmit device. No TDRE=0 ? [3] Dummy read ICDRR. Slave transmit mode Yes No [4] Wait the reception end of 1 byte. RDRF=1 ? [5] Judge the (last receive - 1). Yes [3] Dummy read ICDRR [6] Read the received data, and clear RDRF to 0. [7] Set the acknowledge for the last byte.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) 16.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK detection, STOP recognition, and arbitration lost. Table 16.3 shows the contents of each interrupt request. Table 16.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) 16.6 Bit Synchronous Circuit In master mode, • When SCL is driven to low by the slave device • When the rising speed of SCL is lower by the load of the SCL line (load capacitance or pull-up resistance) This module has a possibility that high level period may be short in the two states described above. Therefore it monitors SCL and communicates by bit with synchronization. Figure 16.18 shows the timing of the bit synchronous circuit and table 16.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) 16.7 Usage Notes (1) Issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check SCLO in the I2C control register B (IICRB) to confirm the fall of the ninth clock. When the start/stop conditions are issued (retransmitted) at the specific timing under the following condition (i) or (ii), such conditions may not be output successfully. This does not occur in other cases.
2 Section 16 I C Bus Interface 2 (IIC2) (Option) When bit manipulation instructions are used to set MST and TRS in succession to specify master transmit while operating in multi-master mode, an arbitration lost may occur, during execution of the bit manipulation instruction to set TRS, with timing that results in a contradictory state in which AL in ICSR is set to 1 and master transmit mode (MST = 1, TRS = 1) is selected as well. The following methods can be used to prevent this from occurring.
Section 17 A/D Converter Section 17 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to sixteen analog input channels to be selected. The block diagram of A/D converter is shown in figure 17.1. 17.1 Features • 10-bit resolution • Sixteen input channels • Conversion time: 7.
Section 17 A/D Converter Module data bus Vref Bus interface Successive approximations register AVCC 10-bit D/A AVSS Internal data bus A D D R A A D D R B A D D R C A D D R D A D D R E A D D R F A D D R G A D D R H A D C S R A D C R AN0 AN1 AN2 + AN3 – AN4 Comparator Control circuit AN6 AN7 AN8 AN9 Multiplexer AN5 Sample-andhold circuit AN10 AN11 AN12 ADI interrupt signal AN13 AN14 Conversion start trigger from 8-bit timer or TPU AN15 ADTRG Legend: ADCR: ADCSR: ADDRA: ADDRB:
Section 17 A/D Converter 17.2 Input/Output Pins Table 17.1 shows the pin configuration of the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. The sixteen analog input pins are divided into two channel sets: channel set 0 (AN0 to AN7) and channel set 1 (AN8 to AN15). Table 17.
Section 17 A/D Converter 17.3 Register Description The A/D converter has the following registers. • A/D data register A (ADDRA) • A/D data register B (ADDRB) • A/D data register C (ADDRC) • A/D data register D (ADDRD) • A/D data register E (ADDRE) • A/D data register F (ADDRF) • A/D data register G (ADDRG) • A/D data register H (ADDRH) • A/D control/status register (ADCSR) • A/D control register (ADCR) 17.3.
Section 17 A/D Converter 17.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit 7 Bit Name ADF Initial Value R/W Description 0 R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion.
Section 17 A/D Converter Bit Bit Name Initial Value R/W Description 3 CH3 0 R/W Channel select 3 to 0 2 CH2 0 R/W 1 CH1 0 R/W Selects analog input together with bits SCANE and SCANS in ADCR. 0 CH0 0 R/W Set the input channel when conversion is stopped (ADST = 0).
Section 17 A/D Converter 17.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion start by an external trigger input. Bit Bit Name Initial Value R/W Description 7 TRGS1 0 R/W Timer Trigger Select 1 and 0 6 TRGS0 0 R/W These bits select enabling or disabling of the start of A/D conversion by a trigger signal.
Section 17 A/D Converter 17.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR to halt A/D conversion. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 17.4.
Section 17 A/D Converter 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion of the first channel in the group starts again. 4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters wait state.
Section 17 A/D Converter (1) φ Address (2) Write signal Input sampling timing ADF tD tSPL tCONV Legend: (1) : ADCSR write cycle (2) : ADCSR address tD : A/D conversion start delay time tSPL : Input sampling time tCONV : A/D conversion time Figure 17.2 A/D Conversion Timing Table 17.
Section 17 A/D Converter Table 17.4 A/D Conversion Time (Scan Mode) CKS1 CKS0 Conversion Time (State) 0 0 512 (Fixed) 1 256 (Fixed) 0 128 (Fixed) 1 64 (Fixed) 1 17.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion.
Section 17 A/D Converter 17.5 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 enables an ADI interrupt requests while the bit ADF in ADCSR is set to 1 after A/D conversion is completed. The DTC or DMAC can be activated by an ADI interrupt. Having the converted data read by the DTC or DMAC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. Table 17.
Section 17 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 17.4 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 17.5 A/D Conversion Accuracy Definitions Rev.7.00 Mar.
Section 17 A/D Converter 17.7 Usage Notes 17.7.1 Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 24, Power-Down Modes. 17.7.
Section 17 A/D Converter 17.7.3 Influences on Absolute Precision Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. 17.7.
Section 17 A/D Converter If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN15) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage.
Section 18 D/A Converter Section 18 D/A Converter 18.1 Features D/A converter features are listed below. • 8-bit resolution • Output channels: Six channels for the H8S/2378 0.18μm F-ZTAT Group, H8S/2378R 0.
Section 18 D/A Converter Internal data bus Bus interface Module data bus Vref AVCC DACR45 DACR23 DADR5 DADR4 DADR3 D/A DACR01 DA2 8-bit DADR2 DA3 DADR1 DA4 DADR0 DA5 DA1 DA0 AVSS Control circuit Legend: DADR0: DADR1: DADR2: DADR3: DADR4: DADR5: DACR01: DACR23: DACR45: D/A data register 0 D/A data register 1 D/A data register 2 D/A data register 3 D/A data register 4 D/A data register 5 D/A control register 01 D/A control register 23 D/A control register 45 Figure 18.
Section 18 D/A Converter Internal data bus Bus interface Module data bus Vref D/A DADR3 8-bit DA2 DADR2 DA3 DACR23 AVCC AVSS Control circuit Legend: DADR2: D/A data register 2 DADR3: D/A data register 3 DACR23: D/A control register 23 Figure 18.2 Block Diagram of D/A Converter for H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R Rev.7.00 Mar.
Section 18 D/A Converter 18.2 Input/Output Pins Table 18.1 shows the pin configuration of the D/A converter. Table 18.
Section 18 D/A Converter 18.3 Register Descriptions The D/A converter has the following registers. • D/A data register 0 (DADR0)* • D/A data register 1 (DADR1)* • D/A data register 2 (DADR2) • D/A data register 3 (DADR3) • D/A data register 4 (DADR4)* • D/A data register 5 (DADR5)* • D/A control register 01 (DACR01)* • D/A control register 23 (DACR23) • D/A control register 45 (DACR45)* Note: * Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R. 18.3.
Section 18 D/A Converter • DACR01 (Available only for the H8S/2377, H8S/2377R, H8S/2378 0.18μm F-ZTAT Group, and H8S/2378R 0.18μm F-ZTAT Group) Bit Bit Name Initial Value R/W Description 7 DAOE1 0 R/W D/A Output Enable 1 Controls D/A conversion and analog output. 0: Analog output (DA1) is disabled 1: Channel 1 D/A conversion is enabled; analog output (DA1) is enabled 6 DAOE0 0 R/W D/A Output Enable 0 Controls D/A conversion and analog output.
Section 18 D/A Converter • DACR23 Bit Bit Name Initial Value R/W Description 7 DAOE3 0 R/W D/A Output Enable 3 Controls D/A conversion and analog output. 0: Analog output (DA3) is disabled 1: Channel 3 D/A conversion is enabled; analog output (DA3) is enabled 6 DAOE2 0 R/W D/A Output Enable 2 Controls D/A conversion and analog output.
Section 18 D/A Converter • DACR45 (Available only for the H8S/2377, H8S/2377R, H8S/2378 0.18μm F-ZTAT Group, and H8S/2378R 0.18μm F-ZTAT Group) Bit Bit Name Initial Value R/W Description 7 DAOE4 0 R/W D/A Output Enable 5 Controls D/A conversion and analog output. 0: Analog output (DA5) is disabled 1: Channel 5 D/A conversion is enabled; analog output (DA5) is enabled 6 DAOE5 0 R/W D/A Output Enable 4 Controls D/A conversion and analog output.
Section 18 D/A Converter 18.4 Operation The D/A converter includes D/A conversion circuits for six channels*1, each of which can operate independently. When DAOE bit in DACR01*2, DACR23, or DACR45*3 is set to 1, D/A conversion is enabled and the conversion result is output. The operation example concerns D/A conversion on channel 2. Figure 18.4 shows the timing of this operation. [1] Write the conversion data to DADR2. [2] Set the DAOE2 bit in DACR23 to 1. D/A conversion is started.
Section 18 D/A Converter DADR2 write cycle DADR2 write cycle DACR23 write cycle DACR23 write cycle φ Address Conversion data 1 DADR2 Conversion data 2 DAOE2 DA2 Conversion result 2 Conversion result 1 High-impedance state tDCONV tDCONV Legend: tDCONV: D/A conversion time Figure 18.3 Example of D/A Converter Operation 18.5 18.5.
Section 19 RAM Section 19 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on the system control register (SYSCR), refer to section 3.2.2, System Control Register (SYSCR). Part No.
Section 19 RAM Rev.7.00 Mar.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) Section 20 Flash Memory (0.35-μm F-ZTAT Version) The features of the flash memory included in the flash memory version are summarized below. The block diagram of the flash memory is shown in figure 20.1. 20.1 Features • Size Product Classification ROM Size ROM Address H8S/2377 HD64F2377 384 kbytes H'000000 to H'05FFFF (Modes 3, 4, and 7) H8S/2377R HD64F2377R • Programming/erase methods The flash memory is programmed 128 bytes at a time.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) Internal address bus Module bus Internal data bus (16 bits) FLMCR1 FLMCR2 Bus interface/controller EBR1 Operating mode Mode pins EBR2 SYSCR Flash memory Legend: FLMCR1: FLMCR2: EBR1: EBR2: SYSCR: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 System control register Figure 20.1 20.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) =0 = ES R SWE = 0 SWE = 1 User program mode RES = 0 RES 0 User mode (on-chip ROM enabled) Reset state =1 MD0 = 1, MD1 = 1, MD2 = 0 MD2 RES = 0 MD0 = 0, MD1 = 0, MD2 = 0, P50 = 0, P51 = 0, P52 = 1 Programmer mode Boot mode On-board programming mode Note: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. Figure 20.2 Flash Memory State Transitions Table 20.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) 1. Initial state (1) the program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. 2.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) 20.3 Block Configuration Figure 20.5 shows the block configuration of 384-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The 384kbyte flash memory is divided into 64 kbytes (5 blocks), 32 kbytes (1 block), and 4 kbytes (8 blocks). Erasing is performed in these divided units.
Section 20 Flash Memory (0.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) 20.4 Input/Output Pins Table 20.2 shows the pin configuration of the flash memory. Table 20.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) Bit Bit Name Initial Value R/W Description 7 ⎯ 0/1 R This bit is reserved. This bit is always read as 0 in modes 1 and 2. This bit is always read as 1 in modes 3 to 7. 6 SWE 0 R/W Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, other FLMCR1 register bits and all EBR1 and EBR2 bits cannot be set.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) 20.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. When the SWE bit in FLMCR1 is cleared to 0, FLMCR2 is initialized to H'00. FLMCR2 is a read-only register, and should not be written to. Bit Bit Name Initial Value R/W Description 7 FLER 0 R Indicates that an error has occurred during an operation on flash memory (programming or erasing).
Section 20 Flash Memory (0.35-μm F-ZTAT Version) 20.5.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Set only one bit in EBR1 and EBR2 together (do not set more than one bit at the same time). Setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0. For details, see table 20.3.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) 20.5.4 Erase Block Register 2 (EBR2) EBR2 specifies the flash memory erase area block. EBR2 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Set only one bit in EBR2 and EBR1 together (do not set more than one bit at the same time). Setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0. For details, see table 20.3.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) Table 20.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) 20.6 On-Board Programming Modes In an on-board programming mode, programming, erasing, and verification for the on-chip flash memory can be performed. There are two on-board programming modes: boot mode and user program mode. Table 20.4 shows how to select boot mode. User program mode can be selected by setting the control bits by software. For a diagram that shows mode transitions of flash memory, see figure 20.2. Table 20.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) 3. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 20.7, Flash Memory Programming/Erasing. 4. Before branching to the programming control program, the chip terminates transfer operations by the SCI_1 (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) Host Operation Communication Contents Processing Contents Bit rate adjustment Boot mode initiation Item Table 20.5 Boot Mode Operation LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Continuously transmits data H'00 at specified bit rate. H'00, H'00 . . . H'00 H'00 Transmits data H'55 when data H'00 is received error-free. • Measures low-level period of receive data H'00.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) Table 20.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps 8 to 25 MHz 9,600 bps 8 to 25 MHz 20.6.2 User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase program.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) 20.7 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 and FLMCR2 setting, the flash memory operates in one of the following four modes: program mode, erase mode, program-verify mode, and erase-verify mode.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) Start of programming Write pulse application subroutine Write pulse application Start Enable WDT Set SWE bit in FLMCR1 Wait (x) μs *6 Store 128-byte program data in program data area and reprogram data area *4 Set PSU bit in FLMCR1 Wait (y) μs *6 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) 20.7.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 20.8 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block registers (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time.
Section 20 Flash Memory (0.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) 20.8 Program/Erase Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 20.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset (including an overflow reset by the WDT) or standby mode.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is forcibly aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, since PV and EV bit setting is enabled, and a transition can be made to verify mode. The error protection state can be canceled by a reset or in hardware standby mode. 20.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) 20.11 Usage Notes Precautions concerning the use of on-board programming mode and programmer mode are summarized below. 1. Use the specified voltages and timing for programming and erasing. Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas microcomputer device type with 512-kbyte on-chip flash memory (FZTAT512V3A).
Section 20 Flash Memory (0.35-μm F-ZTAT Version) 6. Do not perform additional programming. Erase the memory before reprogramming. In on-board programming, perform only one programming operation on a 128-byte programming unit block. In programmer mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. 7. Before programming, check that the chip is correctly mounted in the PROM programmer.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) Wait time: x Programming/ erasing possible Wait time: 100 μs φ Min. 0 μs tOSC1 VCC MD2 to MD0*1 tMDS*3 RES SWE set SWE cleared SWE bit (1) Boot Mode Wait time: x Programming/ erasing possible Wait time: 100 μs φ Min.
Section 20 Flash Memory (0.
Section 20 Flash Memory (0.35-μm F-ZTAT Version) Rev.7.00 Mar.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Section 21 Flash Memory (0.18-μm F-ZTAT Version) The flash memory has the following features. Figure 21.1 shows a block diagram of the flash memory. 21.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) • Programming/erasing time The flash memory programming time is 1 ms (typ) in 128-byte simultaneous programming and 8 µs per byte. The erasing time is 750 ms (typ) per 64-kbyte block. ⎯ User branch The program processing is performed in 128-byte units. It consists the program pulse application, verify read, and several other steps. Erasing is performed in one divided-block units and consists of several steps.
Section 21 Flash Memory (0.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 21.1.1 Operating Mode When the mode pins are set in the reset state and a reset start is performed, the MCU transitions to an operating mode as shown in figure 21.2. • Flash memory cannot be read, programmed, or erased in ROM invalid mode. • Flash memory can be read in user mode, but cannot be programmed or erased. • Flash memory can be read, programmed, or erased on the board only in user program mode, user boot mode, and boot mode.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 21.1.2 Mode Comparison The comparison table of programming and erasing related items about boot mode, user program mode, user boot mode, and PROM mode is shown in table 21.1. Table 21.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 21.1.3 Flash MAT Configuration This LSI’s flash memory is configured by the 256-kbyte/384-kbyte/512-kbyte user MAT and 8kbyte user boot MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when the program execution or data access is performed between two MATs, the MAT must be switched by using FMATS. The user MAT or user boot MAT can be read in all modes if it is in ROM valid mode.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 21.1.4 Block Division The user MAT is divided into 64 kbytes (seven blocks), 32 kbytes (one block), and 4 kbytes (eight blocks) as shown in figure 21.4. The user MAT can be erased in this divided-block units and the erase-block number of EB0 to EB15 is specified when erasing.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 21.1.5 Programming/Erasing Interface Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and specifying the program address/data and erase block by using the interface register/parameter. The procedure program is made by the user in user program mode and user boot mode. An overview of the procedure is given as follows. For details, see section 21.4.2, User Program Mode.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 2. Download of on-chip program The on-chip program is automatically downloaded by setting the SCO bit in the flash key register (FKEY) and the flash control register (FCCS) of the programming/erasing interface register. The flash memory is replaced to the embedded program storage area when downloading.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 21.2 Input/Output Pins Table 21.2 shows the flash memory pin configuration. Table 21.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 21.3 Register Descriptions The registers/parameters which control flash memory are shown as follows.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Table 21.3 Register/Parameter and Target Mode InitialiDownload zation Programming/erasing interface register Read FCCS ⎯ ⎯ ⎯ ⎯ FPCS ⎯ ⎯ ⎯ ⎯ FECS ⎯ ⎯ ⎯ ⎯ FKEY ⎯ FMATS Programming/erasing interface parameter Programming Erasure ⎯ ⎯ *1 *1 ⎯ *2 FTDAR ⎯ ⎯ ⎯ ⎯ DPFR ⎯ ⎯ ⎯ ⎯ FPFR ⎯ ⎯ FPEFEQ ⎯ ⎯ ⎯ ⎯ FUBRA ⎯ ⎯ ⎯ ⎯ FMPAR ⎯ ⎯ ⎯ ⎯ FMPDR ⎯ ⎯ ⎯ ⎯ FEBS ⎯ ⎯ ⎯ ⎯ Notes: 1.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Bit Bit Name Initial Value R/W Description 7 ⎯ 1 R Reserved This bit is always read as 0. The write value should always be 1. 6, 5 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 FLER 0 R Flash Memory Error Indicates an error occurs during programming and erasing flash memory. When FLER is set to 1, flash memory enters the error protection state.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Bit Bit Name Initial Value R/W Description 3 to 1 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 SCO 0 (R)/W Source Program Copy Operation Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically downloaded in the on-chip RAM specified by FTDAR.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) • Flash Program Code Select Register (FPCS) FPCS selects the on-chip programming program to be downloaded. Bit Bit Name Initial Value R/W Description 7 to 1 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 PPVS 0 R/W Program Pulse Verify Selects the programming program.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) • Flash Key Code Register (FKEY) FKEY is a register for software protection that enables download of on-chip program and programming/erasing of flash memory. Before setting the SCO bit to 1 in order to download on-chip program or executing the downloaded programming/erasing program, these processing cannot be executed if the key code is not written.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) • Flash MAT Select Register (FMATS) FMATS specifies whether user MAT or user boot MAT is selected. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 0/1* 0 0/1* 0 0/1* 0 0/1* 0 R/W R/W R/W R/W R/W R/W R/W R/W MAT Select These bits are in user-MAT selection state when the value other than H'AA is written and in user-boot-MAT selection state when H'AA is written.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) • Flash Transfer Destination Address Register (FTDAR) FTDAR is a register that specify the address to download an on-chip program. This register must be specified before setting the SCO bit in FCCS to 1. Bit Bit Name Initial Value R/W 7 TDER 0 R/W Description Transfer Destination Address Setting Error This bit is set to 1 when the address specified by bits TDA6 to TDA0, which is the start address to download an on-chip program, is over the range.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 21.3.2 Programming/Erasing Interface Parameter The programming/erasing interface parameter specifies the operating frequency, storage place for program data, programming destination address, and erase block and exchanges the processing result for the downloaded on-chip program. This parameter uses the general registers of the CPU (ER0 and ER1) or the on-chip RAM area. The initial value is undefined at a power-on reset or in hardware standby mode.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Table 21.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Bit Bit Name Initial Value R/W Description 7 to 3 ⎯ ⎯ ⎯ Unused 2 SS ⎯ R/W Return 0 Source Select Error Detect Only one type for the on-chip program which can be downloaded can be specified. When more than two types of the program are selected, the program is not selected, or the program is selected without mapping, error is occurred.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (2) Programming/Erasing Initialization The on-chip programming/erasing program to be downloaded includes the initialization program. The specified period pulse must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. The operating frequency of the CPU must be set.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (b) Flash user branch address setting parameter (FUBRA: general register ER1 of CPU) This parameter sets the user branch destination address. A specified user program can be used to perform programming or erasing of processing units of predetermined size. When using the user branch function, set the flash user branch enable bits in FPEFEQ to H'AA55 in addition to the settings in this register.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (c) Flash pass/fail parameter (FPFR: general register R0L of CPU) This parameter indicates the return value of the initialization result. Bit Bit Name Initial Value R/W Description 7 to 3 ⎯ ⎯ ⎯ Unused Return 0 2 BR ⎯ R/W User Branch Error Detect (BR) Returns the check result whether the specified user branch destination address is in the area other than the storage area of the programming/erasing program which has been downloaded.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) When data to be programmed does not satisfy 128 bytes, the 128-byte program data must be prepared by filling with the dummy code H'FF. The start address of the area in which the prepared program data is stored must be stored in a general register ER0. This parameter is called as FMPDR (flash multipurpose data destination area parameter). For details on the program processing procedure, see section 21.4.2, User Program Mode.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (c) Flash pass/fail parameter (FPFR: general register R0L of CPU) This parameter indicates the return value of the program processing result. Bit Bit Name Initial Value R/W Description 7 ⎯ ⎯ ⎯ Unused Return 0. 6 MD ⎯ R/W Programming Mode Related Setting Error Detect Returns the check result that the error protection state is not entered. When the error protection state is entered, 1 is written to this bit.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Bit Bit Name Initial Value R/W Description 2 WD ⎯ R/W Write Data Address Detect When the address in the flash memory area is specified as the start address of the storage destination of the program data, an error occurs.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (a) Flash erase block select parameter (FEBS: general register ER0 of CPU) This parameter specifies the erase-block number. Bit Bit Name Initial Value R/W Description 31 to 8 ⎯ ⎯ ⎯ Unused These bits should be cleared to H'0. 7 to 0 Note: EBN7 to EBN0 * ⎯ R/W Erase Block Number Set an erase-block number within the range from 0 to 15. H'00 corresponds to the EB0 block and H'0F corresponds to the EB15 block.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Bit Bit Name Initial Value R/W Description 5 EE ⎯ R/W Erasure Execution Error Detect 1 is returned to this bit when the user MAT could not be erased or when flash-memory related register settings are partially changed on returning from the user branch processing. If this bit is set to 1, there is a high possibility that the user MAT is partially erased. In this case, after removing the error factor, erase the user MAT.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) However, the vector table can be read from the on-chip RAM by the FVACR setting. FVACR is initialized to H'00 at a power-on reset or in hardware standby mode. All interrupts including NMI must be prohibited in the programming/erasing processing or during downloading on-chip program. When the NMI interrupt is necessary, FVACR must be set and the interrupt exception processing routine must be set in the on-chip RAM space or in the external space.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 21.4 On-Board Programming Mode When the pin is set in on-board programming mode and the reset start is executed, the on-board programming state that can program/erase the on-chip flash memory is entered. On-board programming mode has three operating modes: user programming mode, user boot mode, and boot mode. For details of the pin setting for entering each mode, see table 21.5.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) This LSI Host Boot Control command, program data programming tool and program data Reply response Control command, analysis execution software (on-chip) Flash memory RxD1 On-chip SCI1 TxD1 On-chip RAM Figure 21.6 System Configuration in Boot Mode (1) SCI Interface Setting by Host When boot mode is initiated, this LSI measures the low period of asynchronous SCI-communication data (H'00), which is transmitted consecutively by the host.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Table 21.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI Bit Rate of Host System Clock Frequency 9,600 bps 8 to 25 MHz 19,200 bps 8 to 25 MHz (2) State Transition Diagram The overview of the state transition diagram after boot mode is initiated is shown in figure 21.8. 1. Bit rate adjustment After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host. 2.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) programming/erasing command. The erasure must be used when the specified block is programmed without a reset start after programming is executed in boot mode. When programming can be executed by only one operation, all blocks are erased before the state for waiting programming/erasing/other command is entered. The erasing operation is not required. ⎯ There are many commands other than programming/erasing.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 21.4.2 User Program Mode The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be programmed/erased.) Programming/erasing is executed by downloading the program in the microcomputer. The overview flow is shown in figure 21.9. High voltage is applied to internal flash memory during the programming/erasing processing. Therefore, transition to reset or hardware standby must not be executed.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (1) On-Chip RAM Address Map when Programming/Erasing Is Executed Parts of the procedure program that are made by the user, like download request, programming/erasing procedure, and determination of the result, must be executed in the on-chip RAM. The on-chip program that is to be downloaded is all in the on-chip RAM. Note that area in the on-chip RAM must be controlled so that these parts do not overlap. Figure 21.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (2) Programming Procedure in User Program Mode The procedures for download, initialization, and programming are shown in figure 21.11. 1. Disable interrupts and bus master operation other than CPU Set FKEY to H'A5 2. Set FKEY to H'5A 10. Set SCO to 1 and execute download 3. Set parameters to ER1 and ER0 (FMPAR and FMPDR) 11. Clear FKEY to 0 4. Programming JSR FTDAR setting + 16 12.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 21.4.4, Procedure Program and Storable Area for Programming Data. The following description assumes the area to be programmed on the user MAT is erased and program data is prepared in the consecutive area. When erasing is not executed, erasing is executed before writing.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) ⎯ The user-MAT space is switched to the on-chip program storage area. ⎯ After the selection condition of the download program and the FTDAR setting are checked, the transfer processing to the on-chip RAM specified by FTDAR is executed. ⎯ The SCO bits in FPCS, FECS, and FCCS are cleared to 0. ⎯ The return value is set to the DPFR parameter. ⎯ After the on-chip program storage area is returned to the user-MAT space, the user procedure program is returned.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) ⎯ If the value of the DPFR parameter is different from before downloading, check the SS bit (bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program selection and FKEY setting were normal, respectively. 6. The FPEFEQ and FUBRA parameters are set for initialization. ⎯ The current frequency of the CPU clock is set to the FPEFEQ parameter (general register ER0).
Section 21 Flash Memory (0.18-μm F-ZTAT Version) ⎯ Interrupts can be accepted during the execution of the initialization program. The program storage area and stack area in the on-chip RAM and register values must not be destroyed. 8. The return value in the initialization program, FPFR (general register R0L) is determined. 9. All interrupts and the use of a bus master other than the CPU are prohibited. The specified voltage is applied for the specified time when programming or erasing.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 12. Programming There is an entry point of the programming program in the area from the start address specified by FTDAR + 16 bytes of the on-chip RAM. The subroutine is called and programming is executed by using the following steps. MOV.L #DLTOP+16,ER2; Set entry address to ER2 JSR @ER2; Call programming routine NOP ⎯ The general registers other than ER0 and ER1 are held in the programming program. ⎯ R0L is a return value of the FPFR parameter.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) ⎯ Only perform programming finished processing once per block. Even if multiple 128-byte programming operations have been performed to the same block, programming finished processing should only be carried out once. (Due not perform programming finished processing multiple times.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (3) Erasing Procedure in User Program Mode The procedures for download, initialization, and erasing are shown in figure 21.12. Start erasing procedure program a Set FKEY to H'A5 Set FKEY to H'5A Set SCO to 1 and execute download Set FEBS parameter 2. Erasing JSR FTDAR setting + 16 3. Clear FKEY to 0 DPFR = 0? Yes 4.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) A single divided block is erased by one erasing processing. For block divisions, refer to figure 21.4. To erase two or more blocks, update the erase block number and perform the erasing processing for each block. 1. Select the on-chip program to be downloaded Set the EPVB bit in FECS to 1. Several programming/erasing programs cannot be selected at one time.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 5. Determine whether erasure of the necessary blocks has completed. If more than one block is to be erased, update the FEBS parameter and repeat steps 3 to 5. Blocks that have already been erased can be erased again. 6. After erasure completes, clear FKEY and specify software protection.
Section 21 Flash Memory (0.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) MAT is being programmed. Because the user boot MAT is hidden while the user MAT is being programmed, the procedure program must be located in an area other than flash memory. After programming completes, switch the MATs again to return to the first state. MAT switching is enabled by writing a specific value to FMATS. However note that while the MATs are being switched, the LSI is in an unstable state, e.g.
Section 21 Flash Memory (0.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 21.4.4, Procedure Program and Storable Area for Programming Data. 21.4.4 Procedure Program and Storable Area for Programming Data In the descriptions in the previous section, the programming/erasing procedure programs and storable areas for program data are assumed to be in the on-chip RAM.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Boot MAT. Please make sure you know which MAT is selected when switching between them. 8. When the data storable area indicated by programming parameter FMPDR is within the flash memory area, an error will occur even when the data stored is normal. Therefore, the data should be transferred to the on-chip RAM to place the address that FMPDR indicates in an area other than the flash memory.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Table 21.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Storable/Executable Area User MAT External Space (Expanded Mode) Execution of Programming × × Determination of Program Result × Operation for Program Error × Operation for FKEY Clear × Item Note: * On-chip RAM Selected MAT User MAT Embedded Program Storage Area Transferring the data to the on-chip RAM enables this area to be used. Rev.7.00 Mar.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Table 21.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Storable /Executable Area Item On-chip RAM User MAT Operation for Erasure Error × Operation for FKEY Clear × External Space (Expanded Mode) Selected MAT User MAT Embedded Program Storage Area Rev.7.00 Mar.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Table 21.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Storable/Executable Area Item On-chip RAM User Boot MAT Operation for Settings of Program Parameter × Execution of Programming × Determination of Program Result × Operation for Program Error External Space (Expanded Mode) Selected MAT User MAT User Boot MAT Embedded Program Storage Area × ×* 2 Operation for FKEY Clear × Switching MATs by FMATS × × Notes: 1. Transferring the data to the on-chip RAM enables this area to be used. 2.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Table 21.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Storable/Executable Area User Boot MAT External Space (Expanded Mode) Execution of Erasure × × Determination of Erasure Result × Operation for Erasure Error ×* Operation for FKEY Clear × Switching MATs by FMATS × Item Note: * On-chip RAM Selected MAT User MAT User Boot MAT Embedded Program Storage Area × Switching FMATS by a program in the on-chip RAM enables this area to be used. Rev.7.00 Mar.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 21.5 Protection There are two kinds of flash memory program/erase protection: hardware and software protection. 21.5.1 Hardware Protection Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state, the downloading of a on-chip program and initialization are possible.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 21.5.2 Software Protection Software protection is set up by disabling the downloading of on-chip programs for programming and erasing or by means of a key code register. Table 21.10 Software Protection Function to be Protected Item Description Protection by the SCO bit • The program/erase-protected state is entered by clearing the SCO bit in FCCS which disables the downloading of the programming/erasing programs.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) The FLER bit is set in the following conditions: 1. When an interrupt such as NMI occurs during programming/erasing. 2. When the flash memory is read during programming/erasing (including a vector read or an instruction fetch). 3. When a SLEEP instruction (including software-standby mode) is executed during programming/erasing. 4. When a bus master other than the CPU such as the DMAC or DTC gets bus mastership during programming/erasing.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 21.6 Switching between User MAT and User Boot MAT It is possible to alternate between the user MAT and user boot MAT. However, the following procedure is required because these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT should take place in boot mode or PROM mode.) 1. MAT switching by FMATS should always be executed from the on-chip RAM. 2.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 21.7 Programmer Mode Along with its on-board programming mode, this LSI also has a PROM mode as a further mode for the writing and erasing of programs and data. In the PROM mode, a general-purpose PROM programmer can freely be used to write programs to the on-chip ROM. Program/erase is possible on the user MAT and user boot MAT. The PROM programmer must support Renesas microcomputers with 512-kbyte flash memory as a device type.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Reset Bit-rate-adjustment state Inquiry/response wait Response Inquiry Operations for inquiry and selection Transition to programming/erasing Operations for response Operations for erasing user MATs and user boot MATs Programming/erasing wait Programming Operations for programming Erasing Checking Operations for erasing Operations for checking Figure 21.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Host Boot Program H'00 (30 times maximum) Measuring the 1-bit length H'00 (Completion of adjustment) H'55 H'E6 (Boot response) H'FF (error) Figure 21.18 Bit-Rate-Adjustment Sequence (3) Communications Protocol After adjustment of the bit rate, the protocol for communications between the host and the boot program is as shown below. 1. One-byte commands and one-byte responses These commands and responses are comprised of a single byte.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) One-byte command or one-byte response Command or response n-byte Command or n-byte response Data Size Checksum Command or response Error response Error code Error response 128-byte programming Data (n bytes) Address Checksum Command Memory read response Size Data Response Checksum Figure 21.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (4) Inquiry and Selection States The boot program returns information from the flash memory in response to the host’s inquiry commands and sets the device code, clock mode, and bit rate in response to the host’s selection command. Inquiry and selection commands are listed below. Table 21.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40). The host can choose the needed commands out of the commands and inquiries listed above. The boot program status inquiry command (H'4F) is valid after the boot program has received the programming/erasing transition command (H'40).
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (b) Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (d) Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clockmode information after this setting has been made. The clock-mode selection command should be sent after the device-selection commands.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (e) Multiplication Ratio Inquiry The boot program will return the supported multiplication and division ratios.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (f) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (g) User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) • Area-last address (four byte): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. • SUM (one byte): Checksum (i) Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (k) New Bit-Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Error Response H'BF ERROR • Error response, H'BF, (one byte): Error response to selection of new bit rate • ERROR: (one byte): Error code H'11: Sum checking error H'24: Bit-rate selection error The rate is not available. H'25: Error in input frequency This input frequency is not within the specified range. H'26: Multiplication-ratio error The ratio does not match an available ratio.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 4. Bit rate To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR), and the value(N) in the bit rate register (BRR), which are found from the peripheral operating clock frequency (φ) and bit rate (B), are used to calculate the error rate to ensure that it is less than 4%. If the error is more than 4%, a bit rate error is generated.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (6) Transition to Programming/Erasing State The boot program will transfer the erasing program, and erase the user MATs and user boot MATs in that order. On completion of this erasure, ACK will be returned and will enter the programming/erasing state.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (8) Command Order The order for commands in the inquiry selection state is shown below. 1. A supported device inquiry (H'20) should be made to inquire about the supported devices. 2. The device should be selected from among those described by the returned information and set with a device-selection (H'10) command. 3. A clock-mode inquiry (H'21) should be made to inquire about the supported clock modes. 4.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (9) Programming/Erasing State A programming selection command makes the boot program select the programming method, an 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. The programming/erasing commands are listed below. Table 21.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) After issuing the programming selection command, the host should send the 128-byte programming command. The 128-byte programming command that follows the selection command represents the data programmed according to the method specified by the selection command. When more than 128-byte data is programmed, 128-byte commands should repeatedly be executed. Sending an 128-byte programming command with H'FFFFFFFF as the address will stop the programming.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Response H'06 • Response, H'06, (one byte): Response to user boot-program programming selection When the programming program has been transferred, the boot program will return ACK.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) • Programming Data (128 bytes): Data to be programmed The size is specified in the response to the programming unit inquiry. • SUM (one byte): Checksum Response H'06 • Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) • ERROR: (one byte): Error code H'11: Checksum error H'53: Programming error An error has occurred in programming and programming cannot be continued. (10) Erasure Erasure is performed with the erasure selection and block erasure command. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Command H'48 • Command, H'48, (one byte): Erasure selection Response H'06 • Response, H'06, (one byte): Response for erasure selection After the erasure program has been transferred, the boot program will return ACK.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Command H'58 Size Block number SUM • Command, H'58, (one byte): Erasure • Size, (one byte): The number of bytes that represents the block number This is fixed to 1.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) Error Response H'D2 ERROR • Error response: H'D2 (1 byte): Error response to memory read • ERROR: (1 byte): Error code H'11: Sum check error H'2A: Address error The read address is not in the MAT. H'2B: Size error The read size exceeds the MAT. (12) User-Boot Program Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user-boot program, as a four-byte value.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (14) User Boot MAT Blank Check The boot program will check whether or not all user boot MATs are blank and return the result. Command H'4C • Command, H'4C, (one byte): Blank check for user boot MAT Response H'06 • Response, H'06, (one byte): Response to the blank check of user boot MAT If all user MATs are blank (H'FF), the boot program will return ACK.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) (16) Boot Program State Inquiry The boot program will return indications of its present state and error condition. This inquiry can be made in the inquiry/selection state or the programming/erasing state. Command H'4F • Command, H'4F, (one byte): Response H'5F Size Inquiry regarding boot program’s state Status ERROR SUM • Response, H'5F, (one byte): Response to boot program state inquiry • Size (one byte): The number of bytes. This is fixed to 2.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) • ERROR (one byte): Error status ERROR = 0 indicates normal operation. ERROR = 1 indicates error has occurred. Table 21.
Section 21 Flash Memory (0.18-μm F-ZTAT Version) 21.9 Usage Notes 1. Download time of on-chip program The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 4 kbytes or less. Accordingly, when the CPU clock frequency is 35 MHz, the download for each program takes approximately 60 μs at maximum. 2.
Section 22 Masked ROM Section 22 Masked ROM The H8S/2375 and H8S/2375R have 256 kbytes of masked ROM. The on-chip ROM is connected to the CPU, data transfer controller (DTC), and DMA controller (DMAC) with a 16-bit data bus. The on-chip ROM can be accessed by the CPU, DTC, and DMAC in 8 or 16-bit units. The data in the on-chip ROM can always be accessed in one state. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000001 H'000002 H'000003 H'03FFFE H'03FFFF Figure 22.
Section 22 Masked ROM Rev.7.00 Mar.
Section 23 Clock Pulse Generator Section 23 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ) and internal clocks. The clock pulse generator consists of an oscillator circuit, PLL circuit, and divider. Figure 23.1 shows a block diagram of the clock pulse generator.
Section 23 Clock Pulse Generator Bit Bit Name Initial Value R/W Description 7 PSTOP 0 R/W φ Clock Output Disable Controls φ output. Normal Operation 0: φ output 1: Fixed high Sleep Mode 0: φ output 1: Fixed high Software Standby Mode 0: Fixed high 1: Fixed high Hardware Standby Mode 0: High impedance 1: High impedance All module clock stop mode 0: φ output 1: Fixed high 6 — 0 R/W Reserved The initial value should not be changed.
Section 23 Clock Pulse Generator Bit Bit Name Initial Value R/W Description 2 1 0 SCK2 SCK1 SCK0 0 0 0 R/W R/W R/W System Clock Select 2 to 0 Select the division ratio. 000: 1/1 001: 1/2 010: 1/4 011: 1/8 100: Setting prohibited 101: Setting prohibited 11×: Setting prohibited Legend: ×: Don’t care 23.1.2 PLL Control Register (PLLCR) PLLCR sets the frequency multiplication factor used by the PLL circuit.
Section 23 Clock Pulse Generator 23.2 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 23.2.1 Connecting a Crystal Resonator A crystal resonator can be connected as shown in the example in figure 23.2. Select the damping resistance Rd according to table 23.1. An AT-cut parallel-resonance type should be used. Figure 23.3 shows the equivalent circuit of the crystal resonator.
Section 23 Clock Pulse Generator Table 23.2 Crystal Resonator Characteristics Frequency (MHz) 8 12 16 20 25 RS max (Ω) 80 60 50 40 40 C0 max (pF) 7 7 7 7 7 23.2.2 External Clock Input An external clock signal can be input as shown in the examples in figure 23.4. If the XTAL pin is left open, make sure that parasitic capacitance is no more than 10 pF. When the counter clock is input to the XTAL pin, make sure that the external clock is held high in standby mode. Table 23.
Section 23 Clock Pulse Generator Table 23.3 External Clock Input Conditions VCC = 3.0 V to 3.6 V Item Symbol Min Max Unit Test Conditions External clock input low pulse width tEXL 15 — ns Figure 23.5 External clock input high pulse width tEXH 15 — ns External clock rise time tEXr — 5 ns External clock fall time tEXf — 5 ns Clock low pulse width tCL 0.4 0.6 tcyc Clock high pulse width tCH 0.4 0.6 tcyc tEXH tEXL EXTAL VCC × 0.5 tEXr tEXf Figure 23.
Section 23 Clock Pulse Generator 23.3 PLL Circuit The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 1, 2, or 4. The multiplication factor is set with the STC1 and the STC0 bits in PLLCR. The phase of the rising edge of the internal clock is controlled so as to match that of the rising edge of the EXTAL pin. When the multiplication factor of the PLL circuit is changed, the operation varies according to the setting of the STCS bit in SCKCR.
Section 23 Clock Pulse Generator 23.5 Usage Notes 23.5.1 Notes on Clock Pulse Generator 1. The following points should be noted since the frequency of φ changes according to the settings of SCKCR and PLLCR. Select a clock division ratio that is within the operation guaranteed range of clock cycle time tcyc shown in the AC timing of the Electrical Characteristics. In other words, φ must be set to a value between 8 MHz (minimum) and 33 MHz* (maximum).
Section 23 Clock Pulse Generator 23.5.3 Notes on Board Design When using the crystal resonator, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillation circuit to prevent induction from interfering with correct oscillation. See figure 23.6. Avoid Signal A Signal B This LSI CL2 XTAL EXTAL CL1 Figure 23.6 Note on Board Design for Oscillation Circuit Figure 23.
Section 23 Clock Pulse Generator Rev.7.00 Mar.
Section 24 Power-Down Modes Section 24 Power-Down Modes In addition to the normal program execution state, this LSI has power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and so on.
Section 24 Power-Down Modes Table 24.
Section 24 Power-Down Modes Notes: 1. 2. 3. 4. Halted (Retained) in the table means that internal register values are retained and internal operations are suspended. Halted (Reset) in the table means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). The active or halted state can be selected by means of the MSTP0 bit in MSTPCR.
Section 24 Power-Down Modes 24.1 Register Descriptions The registers relating to the power-down mode are shown below. For details on the system clock control register (SCKCR), refer to section 23.1.1, System Clock Control Register (SCKCR).
Section 24 Power-Down Modes Bit Bit Name Initial Value R/W Description 5, 4 ⎯ All 0 ⎯ Reserved These bits are always read as 0. The initial value should not be changed. 3 2 1 0 STS3 STS2 STS1 STS0 1 1 1 1 R/W R/W R/W R/W Standby Timer Select 3 to 0 These bits select the time the MCU waits for the clock to stabilize when software standby mode is cleared by an external interrupt. With crystal oscillation, refer to table 24.
Section 24 Power-Down Modes 24.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) MSTPCR performs module stop mode control. Setting a bit to 1, the corresponding module enters module stop mode, while clearing the bit to 0 clears the module stop mode.
Section 24 Power-Down Modes • MSTPCRL Bit Bit Name Initial Value R/W Module 7 MSTP7 1 R/W D/A converter (channels 4 and 5)* 6 MSTP6 1 R/W A/D converter 5 MSTP5 1 R/W Serial communication interface 4 (SCI_4) 4 MSTP4 1 R/W Serial communication interface 3 (SCI_3) 3 MSTP3 1 R/W Serial communication interface 2 (SCI_2) 2 MSTP2 1 R/W Serial communication interface 1 (SCI_1) 1 MSTP1 1 R/W Serial communication interface 0 (SCI_0) 0 MSTP0 1 R/W 8-bit timer (TMR) Note:
Section 24 Power-Down Modes • EXMSTPCRL Bit Bit Name Initial Value R/W Module 7 MSTP23 1 R/W ⎯ 6 MSTP22 1 R/W ⎯ 5 MSTP21 1 R/W ⎯ 4 MSTP20 1 R/W I C bus interface 2_1 (IIC2_1) 3 MSTP19 1 R/W I C bus interface 2_0 (IIC2_0) 2 MSTP18 1 R/W ⎯ 1 MSTP17 0 R/W ⎯ 0 MSTP16 1 R/W ⎯ 24.2 Operation 24.2.1 Clock Division Mode 2 2 When bits SCK2 to SCK0 in SCKCR are set to a value from 001 to 101, a transition is made to clock division mode at the end of the bus cycle.
Section 24 Power-Down Modes 24.2.2 Sleep Mode Transition to Sleep Mode: When the SLEEP instruction is executed when the SSBY bit is 0 in SBYCR, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers are retained. Other peripheral functions do not stop. Exiting Sleep Mode: Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins.
Section 24 Power-Down Modes generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. Clearing with the RES Pin: When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling.
Section 24 Power-Down Modes Table 24.2 Oscillation Stabilization Time Settings φ*1 [MHz] Standby STS3 STS2 STS1 STS0 Time 35*2 34*3 33 25 20 13 10 8 Unit 0 µs 0 0 1 1 0 1 1 0 0 1 1 0 1 0 Reserved ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1 Reserved ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 Reserved ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1 Reserved ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 Reserved ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1 64 1.8 1.9 1.9 2.6 3.2 4.9 6.4 8.0 0 512 15.0 15.1 15.5 20.5 25.6 39.4 51.2 64.0 1 1024 29.
Section 24 Power-Down Modes Oscillator φ NMI NMIEG SSBY NMI exception handling NMIEG=1 SSBY=1 Software standby mode (power-down mode) Oscillation stabilization time tOSC2 NMI exception handling SLEEP instruction Figure 24.2 Software Standby Mode Application Example 24.2.4 Hardware Standby Mode Transition to Hardware Standby Mode: When the STBY pin is driven low, a transition is made to hardware standby mode from any mode.
Section 24 Power-Down Modes Clearing Hardware Standby Mode: Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator stabilizes (for details on the oscillation stabilization time, refer to table 24.2).
Section 24 Power-Down Modes (1) Power supply RES (2) Reset period STBY (3) Hardware standby mode Figure 24.4 Hardware Standby Mode Timing when Power Is Supplied 24.2.5 Module Stop Mode Module stop mode can be set for individual on-chip peripheral modules. When the corresponding MSTP bit in MSTPCR or EXMSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently.
Section 24 Power-Down Modes All-module-clocks-stop mode is cleared by an external interrupt (NMI, IRQ0 to IRQ7 pins), RES pin input, or an internal interrupt (8-bit timer, watchdog timer), and the CPU returns to the normal program execution state via the exception handling state. All-module-clocks-stop mode is not cleared if interrupts are disabled, if interrupts other than NMI are masked by the CPU, or if the relevant interrupt is designated as a DTC activation source.
Section 24 Power-Down Modes 24.4.3 EXDMAC, DMAC, and DTC Module Stop Depending on the operating status of the EXDMAC, DMAC, or DTC, the MSTP14 to MSTP13 and may not be set to 1. Setting of the EXDMAC, DMAC, or DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 8, EXDMA Controller (EXDMAC), section 7, DMA Controller (DMAC), and section 9, Data Transfer Controller (DTC).
Section 25 List of Registers Section 25 List of Registers The address list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order) • Registers are listed from the lower allocation addresses. • Reserved addresses are indicated by ⎯ in the register name column. Do not access to reserved addresses.
Section 25 List of Registers Register Name Abbrevia- Number tion of Bits Address Module Data Width Access States DTC mode register A MRA 8 H'BC00 to DTC 16/32 2 DTC source address register SAR 24 H'BFFF 16/32 2 DTC mode register B MRB 8 DTC 16/32 2 DTC destination address register DAR 24 DTC 16/32 2 DTC transfer count register A CRA 16 DTC 16/32 2 DTC transfer count register B DTC 16/32 2 DTC CRB 16 2 ICCRA_0 8 H'FD58 IIC2_0 8 2 2 ICCRB_0 8 H'FD59 IIC2_0
Section 25 List of Registers Register Name Abbrevia- Number tion of Bits Address Module EXDMA transfer count register 3 EDTCR_3 EXDMA mode control register 3 EDMDR_3 32 16 Data Width Access States H'FDF8 EXDMAC_3*3 16 2 H'FDFC EXDMAC_3*3 16 2 EXDMA address control register 3 EDACR_3 16 H'FDFE EXDMAC_3*3 16 2 Interrupt priority register A IPRA 16 H'FE00 INT 16 2 Interrupt priority register B IPRB 16 H'FE02 INT 16 2 Interrupt priority register C IPRC 16 H'FE04 INT 1
Section 25 List of Registers Register Name Abbrevia- Number tion of Bits Address Module Data Width Access States Port F data direction register PFDDR 8 H'FE2E PORT 8 2 Port G data direction register PGDDR 8 H'FE2F PORT 8 2 Port function control register 0 PFCR0 8 H'FE32 PORT 8 2 Port function control register 1 PFCR1 8 H'FE33 PORT 8 2 Port function control register 2 PFCR2 8 H'FE34 PORT 8 2 Port A pull-up MOS control register PAPCR 8 H'FE36 PORT 8 2 Port B pull
Section 25 List of Registers Register Name Abbrevia- Number tion of Bits Address Module Data Width Access States Timer interrupt enable register_3 TIER_3 8 H'FE84 TPU_3 16 2 Timer status register_3 TSR_3 8 H'FE85 TPU_3 16 2 Timer counter_3 TCNT_3 16 H'FE86 TPU_3 16 2 Timer general register A_3 TGRA_3 16 H'FE88 TPU_3 16 2 Timer general register B_3 TGRB_3 16 H'FE8A TPU_3 16 2 Timer general register C_3 TGRC_3 16 H'FE8C TPU_3 16 2 Timer general register D_3 TGRD
Section 25 List of Registers Abbrevia- Number tion of Bits Address Module Data Width Access States Chip select assertion period control registers H CSACRH 8 H'FEC8 BSC 16 2 Chip select assertion period control register L CSACRL 8 H'FEC9 BSC 16 2 Burst ROM interface control register H BROMCRH 8 H'FECA BSC 16 2 Burst ROM interface control register L BROMCRL 8 H'FECB BSC 16 2 Bus control register BCR 16 H'FECC BSC 16 2 DRAM control register L DRAMCR 16 H'FED0 BSC 16 2
Section 25 List of Registers Register Name Abbrevia- Number tion of Bits Address Module Data Width Access States DMA control register 0A DMACR_0A 8 H'FF22 DMAC 16 2 DMA control register 0B DMACR_0B 8 H'FF23 DMAC 16 2 DMA control register 1A DMACR_1A 8 H'FF24 DMAC 16 2 DMA control register 1B DMACR_1B 8 H'FF25 DMAC 16 2 DMA band control register H DMABCRH 8 H'FF26 DMAC 16 2 DMA band control register L DMABCRL 8 H'FF27 DMAC 16 2 DTC enable register A DTCERA 8 H'FF
Section 25 List of Registers Register Name Abbrevia- Number tion of Bits Address Module Data Width Access States Next data enable register L NDERL 8 H'FF49 PPG 8 2 Output data register H PODRH 8 H'FF4A PPG 8 2 Output data register L PODRL 8 H'FF4B PPG 8 2 Next data register H*1 NDRH 8 H'FF4C PPG 8 2 *1 NDRL 8 H'FF4D PPG 8 2 *1 NDRH 8 H'FF4E PPG 8 2 *1 Next data register L NDRL 8 H'FF4F PPG 8 2 Port 1 register PORT1 8 H'FF50 PORT 8 2 Port 2 regist
Section 25 List of Registers Register Name Abbrevia- Number tion of Bits Address Module Data Width Access States Port C data register PCDR 8 H'FF6B PORT 8 2 Port D data register PDDR 8 H'FF6C PORT 8 2 Port E data register PEDR 8 H'FF6D PORT 8 2 Port F data register PFDR 8 H'FF6E PORT 8 2 Port G data register PGDR 8 H'FF6F PORT 8 2 Port H register PORTH 8 H'FF70 PORT 8 2 Port H data register PHDR 8 H'FF72 PORT 8 2 Port H data direction register PHDDR 8
Section 25 List of Registers Register Name Abbrevia- Number tion of Bits Address Module Data Width Access States A/D data register B ADDRB 16 H'FF92 A/D 16 2 A/D data register C ADDRC 16 H'FF94 A/D 16 2 A/D data register D ADDRD 16 H'FF96 A/D 16 2 A/D data register E ADDRE 16 H'FF98 A/D 16 2 A/D data register F ADDRF 16 H'FF9A A/D 16 2 A/D data register G ADDRG 16 H'FF9C A/D 16 2 A/D data register H ADDRH 16 H'FF9E A/D 16 2 A/D control/status register A
Section 25 List of Registers Register Name Abbrevia- Number tion of Bits Address Module Timer control/status register TCSR 8 H'FFBC*2 WDT (Write) Data Width Access States 16 2 16 2 16 2 H'FFBC (Read) Timer counter TCNT 8 H'FFBC*2 WDT (Write) H'FFBD (Read) Reset control/status register RSTCSR 8 H'FFBE*2 WDT (Write) H'FFBF (Read) Timer start register TSTR 8 H'FFC0 TPU 16 2 Timer synchronous register TSYR 8 H'FFC1 TPU 16 2 *5 FLASH 8 2 *5 FLASH 8 2 *5 Flash code co
Section 25 List of Registers Register Name Abbrevia- Number tion of Bits Address Module Data Width Access States Timer general register B_0 TGRB_0 16 H'FFDA TPU_0 16 2 Timer general register C_0 TGRC_0 16 H'FFDC TPU_0 16 2 Timer general register D_0 TGRD_0 16 H'FFDE TPU_0 16 2 Timer control register_1 TCR_1 8 H'FFE0 TPU_1 16 2 Timer mode register_1 TMDR_1 8 H'FFE1 TPU_1 16 2 Timer I/O control register_1 TIOR_1 8 H'FFE2 TPU_1 16 2 Timer interrupt enable register
Section 25 List of Registers 25.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively.
Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SEMR_2 ⎯ ⎯ ⎯ ⎯ ABCS ACS2 ACS1 ACS0 SCI_2 Smart card interface 2 EDSAR_2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ EX DMAC_2 *7 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ EDDAR_2 EDTCR_2 ⎯ ⎯ ⎯
Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 EDMDR_3 EDA BEF EDRAKE ETENDE EDREQS AMS EDIE IRF TCEIE SDIR DTSIZE BGUP ⎯ ⎯ EDACR_3 SAT1 SAT0 SARIE SARA4 SARA3 SARA2 SARA1 SARA0 DAT1 DAT0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0 ⎯ IPRA14 IPRA13 IPRA12 ⎯ IPRA10 IPRA9 IPRA8 ⎯ IPRA6 IPRA5 IPRA4 ⎯ IPRA2 IPRA1 IPRA0 ⎯ IPRB14 IPRB13 IPRB12 ⎯ IPRB10 IPRB9 IPRB8 ⎯ IPRB6 IPRB5 IPRB4 ⎯ IPRB2 IPRB1 IPRB0 ⎯ IPRC14 IPRC13 IPRC12 ⎯ IPRC
Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ISCRL IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA INT IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA IrCR_0 IrE IrCKS2 IrCKS1 IrCKS0 ⎯ ⎯ ⎯ ⎯ P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR PORT P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR P3DDR ⎯ ⎯ P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR P5D
Section 25 List of Registers Register Abbreviation Bit 7 *4 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module RDRF ORER FER PER TEND MPB MPBT SCI_3 Smart card interface 3 SSR_3 SSR_3*5 TDRE TDRE RDRF ORER ERS PER TEND MPB MPBT RDR_3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCMR_3 ⎯ ⎯ ⎯ ⎯ SDIR SINV ⎯ SMIF SMR_4*4 SMR_4*5 C/A CHR PE O/E STOP MP CKS1 CKS0 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 BRR_4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCR_4 TI
Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TPU_4 TCR_4 ⎯ CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_4 ⎯ ⎯ ⎯ ⎯ MD3 MD2 MD1 MD0 TIOR_4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_4 TTGE ⎯ TCIEU TCIEV ⎯ ⎯ TGIEB TGIEA TSR_4 TCFD ⎯ TCFU TCFV ⎯ ⎯ TGFB TGFA TCNT_4 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TGRA_4 Bit15 Bit14 Bit13
Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 BCR BRLE DRAMCR BE Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module BREQ0E ⎯ IDLC ICIS1 ICIS0 WDBE WAITE BSC ⎯ ⎯ ⎯ ⎯ ⎯ ICIS2 ⎯ ⎯ OEE RAST ⎯ CAST ⎯ RMTS2 RMTS1 RMTS0 RCDM DDS EDDS ⎯ MXC2 MXC1 MXC0 DRACCRH DRMI ⎯ TPC1 TPC0 SDWCD ⎯ RCD1 RCD0 DRACCRL ⎯ ⎯ ⎯ ⎯ CKSPE ⎯ RDXC1 RDXC0 REFCR CMF CMIE RCW1 RCW0 ⎯ RTCK2 RTCK1 RTCK0 RFSHE CBRM RLW1 RLW0 SLFRF TPCS2 TPCS1 TPCS0 RTCNT Bit7
Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ETCR_1A Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 DMAC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MAR_1BH ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MAR_1BL Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2
Section 25 List of Registers Register Abbreviation Bit 7 INTCR IER ⎯ Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ⎯ INTM1 INTM0 NMIEG ⎯ ⎯ ⎯ INT IRQ15E IRQ14E IRQ13E IRQ12E IRQ11E IRQ10E IRQ9E IRQ8E IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E ISR IRQ15F IRQ14F IRQ13F IRQ12F IRQ11F IRQ10F IRQ9F IRQ8F IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F SBYCR SSBY OPE ⎯ ⎯ STS3 STS2 STS1 STS0 SCKCR PSTOP ⎯ ⎯ ⎯ STCS SCK2 SCK1 SCK0 SYSCR ⎯
Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PORTA PA6 PA5 PA4 PA3 PA2 PA1 PA0 PORT PA7 PORTB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PORTC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PORTD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PORTE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PORTF PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PORTG ⎯ PG6 PG5 PG4 PG3 PG2 PG1 PG0 P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR P2
Section 25 List of Registers Register Abbreviation Bit 7 *4 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SCI_1, Smart card interface 1 SMR_1 SMR_1*5 C/A GM CHR BLK PE PE O/E O/E STOP BCP1 MP BCP0 CKS1 OKS1 CKS0 OKS0 BRR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCR_1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SSR_1 SSR_1*5 TDRE TDRE RDRF RDRF ORER ORER FER ERS PER PER TEND TEND MPB MPB MPBT MPBT RDR_1 Bit7 Bit6
Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ADCSR ADF ADIE ADST ⎯ CH3 CH2 CH1 CH0 A/D ADCR TRGS1 TRGS0 SCANE SCANS CKS1 CKS0 ⎯ ⎯ DADR0*7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DADR1*7 D/A Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DACR01*7 DAOE1 DAOE0 DAE ⎯ ⎯ ⎯ ⎯ ⎯ DADR2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DADR3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DACR23 DAOE3 DAOE2
Section 25 List of Registers Register Abbreviation Bit 7 *8 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MS4 MS3 MS2 MS1 MS0 FLASH MS7 MS6 MS5 FTDAR*8 TDER TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0 EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 EBR2 ⎯ ⎯ EB13 EB12 EB11 EB10 EB9 EB8 FVACR*8 FVCHGE ⎯ ⎯ ⎯ FVSEL3 FVSEL2 FVSEL1 FVSEL0 FVADRR*8 FVA31 FVA30 FVA29 FVA28 FVA27 FVA26 FVA25 FVA24 FVADRE*8 FVA23 FVA22 FVA21 FVA20 FVA19 FVA18 FVA17 FVA16 FVADRH*8
Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TGRA_1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TPU_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TGRB_1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCR_2 ⎯ CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_2 ⎯ ⎯ ⎯ ⎯ MD3 MD2 MD1 MD0 TIOR_2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_2 TTGE ⎯
Section 25 List of Registers 25.
Section 25 List of Registers Register Abbreviation Reset HighSpeed Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Module EDSAR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized EXDMAC_3 EDDAR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized *1 EDTCR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized EDMDR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized EDACR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IPRA Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IPRB Initialized ⎯ ⎯
Section 25 List of Registers Register Abbreviation Reset Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Module Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PGDDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PFCR0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PFCR1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PFCR2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PAPCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PBPCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PCPCR Initia
Section 25 List of Registers Register Abbreviation Reset HighSpeed Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Module TGRA_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TGRB_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TGRC_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TGRD_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TCR_4 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TMDR_4 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TIOR_4 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ In
Section 25 List of Registers Register Abbreviation Reset HighSpeed Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Module DRAMCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DRACCRH Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DRACCRL Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized REFCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized RTCNT Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized RTCOR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized MAR_0AH Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ I
Section 25 List of Registers Register Abbreviation Reset HighSpeed Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Module DTCERA Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DTCERB Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DTCERC Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DTCERD Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DTCERE Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DTCERF Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DTCERG Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ I
Section 25 List of Registers Register Abbreviation Reset HighSpeed Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Module PORT1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORT2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORT3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORT4 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORT5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORT6 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORT8 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORT9 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORTA ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORTB ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORTC ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORT
Section 25 List of Registers Register Abbreviation Reset HighSpeed Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Module SMR_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized BRR_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SCR_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TDR_0 Initialized ⎯ ⎯ ⎯ Initialized Initialized Initialized Initialized SSR_0 Initialized ⎯ ⎯ ⎯ Initialized Initialized Initialized Initialized RDR_0 Initialized ⎯ ⎯ ⎯ Initialized
Section 25 List of Registers Register Abbreviation Reset HighSpeed Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Module DADR0*2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DADR1*2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DACR01*2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DADR2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DADR3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DACR23 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DADR4*1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Section 25 List of Registers Register Abbreviation Reset HighSpeed Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Module EBR1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized EBR2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized FVACR*2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized FVADRR*2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized FVADRE*2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized FVADRH*2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized FVADRL*2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯
Section 25 List of Registers Register Abbreviation Reset HighSpeed Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Module TCNT_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TGRA_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TGRB_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TPU_2 Notes: 1. Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R. 2. Supported only by the H8S/2378 0.18μm F-ZTAT Group and H8S/2378R 0.18μm F-ZTAT Group. Rev.7.00 Mar.
Section 25 List of Registers Rev.7.00 Mar.
Section 26 Electrical Characteristics Section 26 Electrical Characteristics 26.1 Electrical Characteristics for H8S/2377, H8S/2375, H8S/2373, H8S/2377R, H8S/2375R, and H8S/2373R 26.1.1 Absolute Maximum Ratings Table 26.1 lists the absolute maximum ratings. Table 26.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC −0.3 to +4.3 V Input voltage (except ports 4 and 9) Vin −0.3 to VCC +0.3 V Input voltage (ports 4 and 9) Vin −0.3 to AVCC +0.
Section 26 Electrical Characteristics 26.1.2 DC Characteristics Table 26.2 DC Characteristics (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Symbol Min. Typ. Port 1, port 2, Schmitt VT− VCC × 0.2 ⎯ 2 trigger input P50 to 2P53* , 2 + VT ⎯ ⎯ port 6* , port 8* , voltage 2 * + − PA4 to PA7 , VT − VT VCC × 0.
Section 26 Electrical Characteristics Table 26.3 DC Characteristics (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Symbol Min. Typ. Max. Test Unit Conditions |Iin| ⎯ ⎯ 10.0 μA STBY, NMI, MD2 to MD0 ⎯ ⎯ 1.0 μA Port 4, Port 9 ⎯ ⎯ 1.0 μA Vin = 0.5 to AVCC −0.5 V | ITSI | ⎯ ⎯ 1.0 μA Vin = 0.5 to VCC −0.
Section 26 Electrical Characteristics Item Reference power supply current During A/D and D/A conversion Min. Typ. AICC ⎯ 3.0 6.0 (3.0 V) mA ⎯ 0.01 5.0 μA 2.0 ⎯ ⎯ V Idle RAM standby voltage VRAM Max. Test Unit Conditions Symbol Notes: 1. When the A/D and D/A converters are not used, the AVCC, Vref, and AVSS pins should not be open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. 2. Current consumption values are for VIHmin = VCC −0.2 V and VILmax = 0.
Section 26 Electrical Characteristics 26.1.3 AC Characteristics 3V RL C = 50 pF: ports A to H (except for PH1 when SDRAMφ is in use.) C = 30 pF: ports 1 to 3, P50 to P53, ports 6 and 8, and PH1 (PH1 when SDRAMφ∗ is in use.) LSI output pin C RH RL = 2.4 kΩ RH = 12 kΩ Input/output timing measurement level: 1.5 V (VCC = 3.0 V to 3.6 V) Note: * Not supported by the H8S/2378 Group. Figure 26.1 Output Load Circuit Rev.7.00 Mar.
Section 26 Electrical Characteristics (1) Clock Timing Table 26.5 Clock Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions Clock cycle time tcyc 30.3 125 ns Figure 26.2 Clock pulse high width tCH 10 ⎯ ns Figure 26.
Section 26 Electrical Characteristics (2) Control Signal Timing Table 26.6 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions RES setup time tRESS 200 ⎯ ns Figure 26.
Section 26 Electrical Characteristics (3) Bus Timing Table 26.7 Bus Timing (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions Address delay time TAD ⎯ 20 ns Address setup time 1 TAS1 0.5 × tcyc −13 ⎯ ns Figures 26.7 to 26.22 Address setup time 2 TAS2 1.
Section 26 Electrical Characteristics Table 26.8 Bus Timing (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions WR delay time 1 tWRD1 ⎯ 15 ns WR delay time 2 tWRD2 ⎯ 15 ns Figures 26.7 to 26.22 WR pulse width 1 tWSW1 1.0 × tcyc −13 ⎯ ns WR pulse width 2 tWSW2 1.
Section 26 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions Self-refresh precharge time 1 tRPS1 2.5 × tcyc −20 ⎯ ns Self-refresh precharge time 2 tRPS2 3.0 × tcyc −20 ⎯ ns Figures 26.21 and 26.22 WAIT setup time tWTS 25 ⎯ ns WAIT hold time tWTH 5 ⎯ ns BREQ setup time tBREQS 30 ⎯ ns Figures 26.9 and 26.15 Figure 26.
Section 26 Electrical Characteristics (4) DMAC and EXDMAC Timing Table 26.9 DMAC and EXDMAC Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions DREQ setup time tDRQS 25 ⎯ ns Figure 26.31 DREQ hold time tDRQH 10 ⎯ TEND delay time tTED ⎯ 18 ns Figure 26.
Section 26 Electrical Characteristics (5) Timing of On-Chip Peripheral Modules Table 26.10 Timing of On-Chip Peripheral Modules Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item I/O ports Max. Unit Test Conditions Output data delay time tPWD Symbol Min. ⎯ 40 ns Figure 26.
Section 26 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions A/D converter Trigger input setup time tTRGS 30 ⎯ ns Figure 26.43 IIC2 SCL input cycle time tSCL 12 tCYC +600 ⎯ ns Figure 26.
Section 26 Electrical Characteristics 26.1.4 A/D Conversion Characteristics Table 26.11 A/D Conversion Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Min. Typ. Max. Unit Resolution 10 10 10 Bit Conversion time 8.
Section 26 Electrical Characteristics 26.1.6 Flash Memory Characteristics Table 26.13 Flash Memory Characteristics (0.35-μm F-ZTAT Version) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = 0°C to 75°C (program/erase operating temperature range: regular specifications), Ta = 0°C to 85°C (program/erase operating temperature range: wide-range specifications) Item Symbol Min. Typ. Max.
Section 26 Electrical Characteristics Notes: 1. Follow the program/erase algorithms when making the time settings. 2. Programming time per 128 bytes. (Indicates the total time during which the P bit is set in flash memory control register 1 (FLMCR1). Does not include the program-verify time.) 3. Time to erase one block. (Indicates the time during which the E bit is set in FLMCR1. Does not include the erase-verify time.) 4. Maximum programming time N tP(max) = Σ wait time after P bit setting (z) i=1 5.
Section 26 Electrical Characteristics 26.2 Electrical Characteristics for H8S/2378 26.2.1 Absolute Maximum Ratings Table 26.14 lists the absolute maximum ratings. Table 26.14 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC −0.3 to +4.3 V Vin −0.3 to VCC +0.3 V Input voltage (ports 4 and 9) Vin −0.3 to AVCC +0.3 V Reference power supply voltage Vref −0.3 to AVCC +0.3 V Analog power supply voltage AVCC −0.3 to +4.0 V Analog input voltage VAN −0.
Section 26 Electrical Characteristics 26.2.2 DC Characteristics Table 26.15 DC Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Symbol Item Min. Typ. VT− VCC × 0.2 ⎯ Port 1, port 2, Schmitt 2 * + trigger input P50 to P53 , ⎯ ⎯ 2 2 VT voltage port 6* , port 8* , + − 2 VT − VT VCC × 0.
Section 26 Electrical Characteristics Table 26.16 DC Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Symbol Min. Typ. Max. Test Unit Conditions |Iin| ⎯ ⎯ 10.0 μA STBY, NMI, MD2 to MD0 ⎯ ⎯ 1.0 μA Port 4, Port 9 ⎯ ⎯ 1.0 μA Vin = 0.5 to AVCC −0.5 V | ITSI | ⎯ ⎯ 1.0 μA Vin = 0.5 to VCC −0.
Section 26 Electrical Characteristics Item Symbol Min. Typ. Max. Test Unit Conditions RAM standby voltage VRAM 2.5 ⎯ ⎯ V 5 VCC start voltage* 5 VCC rise slope* VCCstart ⎯ ⎯ 0.8 V SVCC ⎯ ⎯ 20 ms/V Notes: 1. When the A/D and D/A converters are not used, the AVCC, Vref, and AVSS pins should not be open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. 2. Current consumption values are for VIHmin = VCC −0.2 V and VILmax = 0.
Section 26 Electrical Characteristics 26.2.3 AC Characteristics The clock, control signal, bus, DMAC, EXDMAC, and on-chip peripheral function timings are shown below. The measurement conditions of the AC characteristics are shown in figure 26.1. (1) Clock Timing Table 26.18 Clock Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 26 Electrical Characteristics (2) Control Signal Timing Table 26.19 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 35 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions RES setup time tRESS 200 ⎯ ns Figure 26.
Section 26 Electrical Characteristics (3) Bus Timing Table 26.20 Bus Timing (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 35 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions Address delay time TAD Address setup time 1 TAS1 ⎯ 20 ns 0.5 × tcyc −13 ⎯ ns Figures 26.7 to 26.20, 26.25 Address setup time 2 TAS2 1.
Section 26 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions Address read data access time 1 TAA1 ⎯ 1.0 × tcyc −25 ns Address read data access time 2 TAA2 ⎯ 1.5 × tcyc −25 ns Figures 26.7 to 26.20, 26.25 Address read data access time 3 TAA3 ⎯ 2.0 × tcyc −25 ns Address read data access time 4 TAA4 ⎯ 2.5 × tcyc −25 ns Address read data access time 5 TAA5 ⎯ 3.0 × tcyc −25 ns Rev.7.00 Mar.
Section 26 Electrical Characteristics Table 26.21 Bus Timing (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 35 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions WR delay time 1 tWRD1 ⎯ 15 ns WR delay time 2 tWRD2 ⎯ 15 ns Figures 26.7 to 26.20 WR pulse width 1 tWSW1 1.0 × tcyc −13 ⎯ ns WR pulse width 2 tWSW2 1.
Section 26 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions Self-refresh precharge time 1 tRPS1 2.5 × tcyc −20 ⎯ ns Self-refresh precharge time 2 tRPS2 3.0 × tcyc −20 ⎯ ns Figures 26.21 and 26.22 WAIT setup time tWTS 25 ⎯ ns WAIT hold time tWTH 5 ⎯ ns BREQ setup time tBREQS 30 ⎯ ns BACK delay time tBACD ⎯ 15 ns Bus floating time tBZD ⎯ 40 ns BREQO delay time tBRQOD ⎯ 25 ns Rev.7.00 Mar.
Section 26 Electrical Characteristics (4) DMAC and EXDMAC Timing Table 26.22 DMAC and EXDMAC Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 35 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions DREQ setup time tDRQS 25 ⎯ ns Figure 26.31 DREQ hold time tDRQH 10 ⎯ TEND delay time tTED ⎯ 18 ns Figure 26.
Section 26 Electrical Characteristics (5) Timing of On-Chip Peripheral Modules Table 26.23 Timing of On-Chip Peripheral Modules Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 35 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item I/O ports Max. Unit Test Conditions Output data delay time tPWD Symbol Min. ⎯ 40 ns Figure 26.
Section 26 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions A/D converter Trigger input setup time tTRGS 30 ⎯ ns Figure 26.43 IIC2 SCL input cycle time tSCL 12 tCYC +600 ⎯ ns Figure 26.
Section 26 Electrical Characteristics 26.2.4 A/D Conversion Characteristics Table 26.24 A/D Conversion Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 35 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Min. Typ. Max. Unit Resolution 10 10 10 Bit Conversion time 7.
Section 26 Electrical Characteristics 26.2.6 Flash Memory Characteristics Table 26.26 Flash Memory Characteristics (0.18-μm F-ZTAT Version) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = 0°C to 75°C (Programming/Erasing Operating Temperature Range: Normal Specifications), Ta = 0°C to 85°C (Programming/Erasing Operating Temperature Range: Extended Temperature Range Specifications) Item Symbol Min. Typ. Max.
Section 26 Electrical Characteristics 26.3 Electrical Characteristics for H8S/2374, H8S/2372, H8S/2371, H8S/2370, H8S/2378R, H8S/2374R, H8S/2372R, H8S/2371R, H8S/2370R 26.3.1 Absolute Maximum Ratings Table 26.27 lists the absolute maximum ratings. Table 26.27 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC −0.3 to +4.3 V PLLVCC Input voltage (except ports 4 and 9) Vin −0.3 to VCC +0.3 V Input voltage (ports 4 and 9) Vin −0.3 to AVCC +0.
Section 26 Electrical Characteristics 26.3.2 DC Characteristics Table 26.28 DC Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Symbol Item Min. Typ. VT− VCC × 0.2 ⎯ Port 1, port 2, Schmitt 2 * + trigger input P50 to P53 , ⎯ ⎯ 2 2 VT voltage port 6* , port 8* , + − 2 VT − VT VCC × 0.
Section 26 Electrical Characteristics Table 26.29 DC Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Symbol Min. Typ. Max. Test Unit Conditions |Iin| ⎯ ⎯ 10.0 μA STBY, NMI, MD2 to MD0 ⎯ ⎯ 1.0 μA Port 4, Port 9 ⎯ ⎯ 1.0 μA Vin = 0.5 to AVCC −0.5 V | ITSI | ⎯ ⎯ 1.0 μA Vin = 0.5 to VCC −0.
Section 26 Electrical Characteristics Item Symbol Min. Typ. Max. Test Unit Conditions RAM standby voltage VRAM 2.5 ⎯ ⎯ V 5 VCC start voltage* 5 VCC rise slope* VCCstart ⎯ ⎯ 0.8 V SVCC ⎯ ⎯ 20 ms/V Notes: 1. When the A/D and D/A converters are not used, the AVCC, Vref, and AVSS pins should not be open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. 2. Current consumption values are for VIHmin = VCC −0.2 V and VILmax = 0.
Section 26 Electrical Characteristics 26.3.3 AC Characteristics The clock, control signal, bus, DMAC, EXDMAC, and on-chip peripheral function timings are shown below. The measurement conditions of the AC characteristics are shown in figure 26.1. (1) Clock Timing Table 26.31 Clock Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 26 Electrical Characteristics (2) Control Signal Timing Table 26.32 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 34 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions RES setup time tRESS 200 ⎯ ns Figure 26.
Section 26 Electrical Characteristics (3) Bus Timing Table 26.33 Bus Timing (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 34 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions Address delay time TAD Address setup time 1 TAS1 ⎯ 20 ns 0.5 × tcyc −13 ⎯ ns Figures 26.7 to 26.20, 26.25 Address setup time 2 TAS2 1.
Section 26 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions Address read data access time 1 TAA1 ⎯ 1.0 × tcyc −25 ns Address read data access time 2 TAA2 ⎯ 1.5 × tcyc −25 ns Figures 26.7 to 26.20, 26.25 Address read data access time 3 TAA3 ⎯ 2.0 × tcyc −25 ns Address read data access time 4 TAA4 ⎯ 2.5 × tcyc −25 ns Address read data access time 5 TAA5 ⎯ 3.0 × tcyc −25 ns Rev.7.00 Mar.
Section 26 Electrical Characteristics Table 26.34 Bus Timing (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 34 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions WR delay time 1 tWRD1 ⎯ 15 ns WR delay time 2 tWRD2 ⎯ 15 ns Figures 26.7 to 26.20 WR pulse width 1 tWSW1 1.0 × tcyc −13 ⎯ ns WR pulse width 2 tWSW2 1.
Section 26 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions Self-refresh precharge time 1 tRPS1 2.5 × tcyc −20 ⎯ ns Self-refresh precharge time 2 tRPS2 3.0 × tcyc −20 ⎯ ns Figures 26.21 and 26.22 WAIT setup time tWTS 25 ⎯ ns WAIT hold time tWTH 5 ⎯ ns BREQ setup time tBREQS 30 ⎯ ns BACK delay time tBACD ⎯ 15 ns Bus floating time tBZD ⎯ 40 ns BREQO delay time tBRQOD ⎯ 25 ns Figures 26.9 and 26.15 Figure 26.23 Figure 26.
Section 26 Electrical Characteristics (4) DMAC and EXDMAC Timing Table 26.35 DMAC and EXDMAC Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 34 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions DREQ setup time tDRQS 25 ⎯ ns Figure 26.31 DREQ hold time tDRQH 10 ⎯ TEND delay time tTED ⎯ 18 ns Figure 26.
Section 26 Electrical Characteristics (5) Timing of On-Chip Peripheral Modules Table 26.36 Timing of On-Chip Peripheral Modules Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 34 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item I/O ports Max. Unit Test Conditions Output data delay time tPWD Symbol Min. ⎯ 40 ns Figure 26.
Section 26 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions A/D converter Trigger input setup time tTRGS 30 ⎯ ns Figure 26.43 IIC2 SCL input cycle time tSCL 12 tCYC +600 ⎯ ns Figure 26.
Section 26 Electrical Characteristics 26.3.4 A/D Conversion Characteristics Table 26.37 A/D Conversion Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 34 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Min. Typ. Max. Unit Resolution 10 10 10 Bit Conversion time 7.
Section 26 Electrical Characteristics 26.3.6 Flash Memory Characteristics Table 26.39 Flash Memory Characteristics (0.18-μm F-ZTAT Version) (512 kbytes) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = 0°C to 75°C (Programming/Erasing Operating Temperature Range: Normal Specifications), Ta = 0°C to 85°C (Programming/Erasing Operating Temperature Range: Extended Temperature Range Specifications) Item Symbol Min. Typ. Max.
Section 26 Electrical Characteristics Table 26.40 Flash Memory Characteristics (0.18-μm F-ZTAT Version) (384 kbytes) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = 0°C to 75°C (Programming/Erasing Operating Temperature Range: Normal Specifications), Ta = 0°C to 85°C (Programming/Erasing Operating Temperature Range: Extended Temperature Range Specifications) Item Symbol Min. Typ. Max.
Section 26 Electrical Characteristics Table 26.41 Flash Memory Characteristics (0.18-μm F-ZTAT Version) (256 kbytes) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = 0°C to 75°C (Programming/Erasing Operating Temperature Range: Normal Specifications), Ta = 0°C to 85°C (Programming/Erasing Operating Temperature Range: Extended Temperature Range Specifications) Item Symbol Min. Typ. Max.
Section 26 Electrical Characteristics 26.4 Timing Charts 26.4.1 Clock Timing The clock timings are shown below. tcyc tCf tCH φ tCL tCr Figure 26.2 System Clock Timing tcyc tCH tCf φ tCr tCL tcdif tsdcf tsdcr SDRAMφ tSDCH tSDCL Figure 26.3 SDRAMφ Timing Rev.7.00 Mar.
Section 26 Electrical Characteristics EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES φ Figure 26.4 (1) Oscillation Settling Timing Oscillator φ NMI NMIEG SSBY NMI exception handling NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down mode) Oscillation stabilization time tOSC2 SLEEP instruction Figure 26.4 (2) Oscillation Settling Timing Rev.7.00 Mar.
Section 26 Electrical Characteristics 26.4.2 Control Signal Timing The control signal timings are shown below. φ tRESS tRESS RES tRESW Figure 26.5 Reset Input Timing φ tNMIS tNMIH NMI tNMIW tIRQW IRQi (i = 0 to 15)* tIRQS tIRQH IRQ (edge input) tIRQS IRQ (level input) Note: * Necessary for SSIER setting to clear software standby mode. Figure 26.6 Interrupt Input Timing Rev.7.00 Mar.
Section 26 Electrical Characteristics 26.4.3 Bus Timing The bus timings are shown below. T1 T2 φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tASD tAH1 AS tAS1 tRSD1 tRSD1 RD Read (RDNn = 1) tRDS1 tRDH1 tAC5 tAA2 D15 to D0 tAS1 tRSD1 tRSD2 RD Read (RDNn = 0) tAC2 tRDS2 tRDH2 tAA3 D15 to D0 tAS1 tWRD2 tWRD2 tAH1 HWR, LWR tWDD Write tWSW1 tWDH1 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 26.7 Basic Bus Timing: Two-State Access Rev.7.00 Mar.
Section 26 Electrical Characteristics T2 T1 T3 φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tAH1 tASD AS tAS1 tRSD1 tRSD1 RD Read (RDNn = 1) tRDS1 tRDH1 tAC6 tAA4 D15 to D0 tAS1 tRSD1 tRSD2 RD Read (RDNn = 0) tRDS2 tAC4 tRDH2 tAA5 D15 to D0 tAS2 tWRD1 HWR, LWR tWDS1 tWDD Write tAH1 tWRD2 tWSW2 tWDH1 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 26.8 Basic Bus Timing: Three-State Access Rev.7.00 Mar.
Section 26 Electrical Characteristics T1 T2 Tw tWTS tWTH tWTS tWTH T3 φ A23 to A0 CS7 to CS0 AS RD Read (RDNn = 1) D15 to D0 RD Read (RDNn = 0) D15 to D0 HWR, LWR Write D15 to D0 WAIT Figure 26.9 Basic Bus Timing: Three-State Access, One Wait Rev.7.00 Mar.
Section 26 Electrical Characteristics Th T2 T1 Tt φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tAH1 tASD tASD AS tAS3 tAH3 tRSD1 tRSD1 RD Read (RDNn = 1) tAC5 tRDS1 tRDH1 tRSD1 tRSD2 D15 to D0 tAS3 tAH2 RD Read (RDNn = 0) tAC2 tRDS2 tRDH2 D15 to D0 tAS3 tWRD2 tWRD2 tAH3 HWR, LWR tWDD Write tWDS2 tWSW1 tWDH3 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 26.10 Basic Bus Timing: Two-State Access (CS Assertion Period Extended) Rev.7.00 Mar.
Section 26 Electrical Characteristics Th T1 T2 T3 Tt φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tAH1 tASD AS tAS3 tRSD1 tAH3 tRSD1 RD Read (RDNn = 1) tRDS1 tRDH1 tAC6 D15 to D0 tAS3 tAH2 tRSD2 tRSD1 RD Read (RDNn = 0) tRDS2 tRDH2 tAC4 D15 to D0 tAS4 tAH3 tWRD1 HWR, LWR tWDD Write tWRD2 tWDS3 tWSW2 tWDH3 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 26.11 Basic Bus Timing: Three-State Access (CS Assertion Period Extended) Rev.7.00 Mar.
Section 26 Electrical Characteristics T1 T1 T2 T1 φ A23 to A6, A0 tAD A5 to A1 CS7 to CS0 AS tRSD2 RD tAA1 tRDS2 tRDH2 Read D15 to D0 HWR, LWR Figure 26.12 Burst ROM Access Timing: One-State Burst Access Rev.7.00 Mar.
Section 26 Electrical Characteristics T1 T2 T3 T1 T2 φ A23 to A6, A0 tAD A5 to A1 CS7 to CS0 tAH1 tAS1 tASD AS tASD tRSD2 RD Read tAA3 D15 to D0 HWR, LWR Figure 26.13 Burst ROM Access Timing: Two-State Burst Access Rev.7.00 Mar.
Section 26 Electrical Characteristics Tp Tr Tc2 Tc1 φ tAD tAD A23 to A0 tAS3 RAS5 to RAS2 tCSD3 tAH1 tCSD2 tAS2 tPCH2 tAH2 tCASD1 tCASD1 UCAS tCASW1 LCAS tOED1 tOED1 tAC1 OE, RD Read HWR tAA3 tRDS2 tRDH2 tAC4 D15 to D0 OE, RD tWRD2 Write tWCS1 tWCH1 tWRD2 HWR tWDD tWDS1 tWDH2 D15 to D0 AS tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 0 Figure 26.
Section 26 Electrical Characteristics Tp Tr Tc1 Tcw Tcwp Tc2 φ A23 to A0 RAS5 to RAS2 UCAS, LCAS OE, RD Read HWR D15 to D0 UCAS, LCAS OE, RD Write HWR D15 to D0 AS tWTS tWTH tWTS tWTH WAIT DACK0, DACK1 EDACK2, EDACK3 Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 0 Tcw : Wait cycle inserted by programmable wait function Tcwp: Wait cycle inserted by pin wait function Figure 26.15 DRAM Access Timing: Two-State Access, One Wait Rev.7.00 Mar.
Section 26 Electrical Characteristics Tp Tr Tc1 Tc2 Tc1 Tc2 φ A23 to A0 RAS5 to RAS2 tCPW1 UCAS LCAS OE, RD Read HWR tAC3 D15 to D0 OE, RD Write tRCH HWR tRCS1 D15 to D0 AS tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 0 Figure 26.16 DRAM Access Timing: Two-State Burst Access Rev.7.00 Mar.
Section 26 Electrical Characteristics Tp Tr Tc1 Tc3 Tc2 φ tAD tAD A23 to A0 tAS2 RAS5 to RAS2 tCSD3 tAH2 tCSD2 tPCH1 tAS3 tAH3 tCASD1 tCASD2 UCAS tCASW2 LCAS tOED2 tOED1 tAC2 OE, RD Read HWR tAA5 tRDS2 tRDH2 tAC7 D15 to D0 OE, RD Write tWRD2 tWCS2 tWCH2 tWRD2 HWR tWDD tWDS2 tWDH3 D15 to D0 AS tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 0 Figure 26.
Section 26 Electrical Characteristics Tp Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3 φ A23 to A0 RAS5 to RAS0 tCPW2 UCAS LCAS OE, RD Read HWR tAC8 D15 to D0 OE, RD Write tRCH HWR tRCS2 D15 to D0 AS DACK0, DACK1 EDACK2, EDACK3 Note: DACK and EDACK timing: when DDS = 1 and EDDS = 1 RAS timing: when RAST = 1 Figure 26.18 DRAM Access Timing: Three-State Burst Access Rev.7.00 Mar.
Section 26 Electrical Characteristics TRp TRr TRc1 TRc2 φ tCSD1 tCSD2 RAS5 to RAS2 tCSR1 tCASD1 tCASD1 UCAS, LCAS OE Figure 26.19 CAS-Before-RAS Refresh Timing TRp TRrw TRr TRc1 TRcw TRc2 φ tCSD1 tCSD2 RAS5 to RAS2 UCAS, LCAS tCSR2 tCASD1 OE Figure 26.20 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion) Rev.7.00 Mar.
Section 26 Electrical Characteristics Self-refresh TRp TRr TRc TRc DRAM access Tpsr Tp Tr φ tCSD2 tCSD2 RAS5 to RAS2 tRPS2 tCASD1 tCASD1 UCAS, LCAS OE Figure 26.21 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) Self-refresh TRp TRr TRc TRc Tpsr DRAM access Tp Tr φ tCSD2 RAS5 to RAS2 tCASD1 tCSD2 tRPS1 tCASD1 UCAS, LCAS OE Figure 26.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) Rev.7.00 Mar.
Section 26 Electrical Characteristics φ tBREQS tBREQS BREQ tBACD tBACD BACK tBZD tBZD A23 to A0 CS7 to CS0 (RAS5 to RAS2) D15 to D0 AS, RD HWR, LWR UCAS, LCAS, OE Figure 26.23 External Bus Release Timing φ BACK tBRQOD tBRQOD BREQO Figure 26.24 External Bus Request Output Timing Rev.7.00 Mar.
Section 26 Electrical Characteristics Tp Tr Tc1 Tw Tc2 φ SDRAMφ tAD2 Address bus Precharge-sel RAS tCSD4 tCSD4 tCSD4 CAS Read tCSD4 tCSD4 tCSD4 WE CKE tDQMD High tDQMD DQMU, DQML tRDS3 tRDH3 Data bus tCSD4 tCSD4 RAS tCSD4 CAS tCSD4 tCSD4 tCSD4 WE tCSD4 tCSD4 Write CKE High tDQMD DQMU, DQML tDQMD tWDD Data bus tWDH4 Figure 26.25 Synchronous DRAM Basic Access Timing (CAS Latency 2) Rev.7.00 Mar.
Section 26 Electrical Characteristics TRp TRr Software standby TRr2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE tCKED CKE tCKED Figure 26.26 Synchronous DRAM Self-Refresh Timing Rev.7.00 Mar.
Section 26 Electrical Characteristics Tp Tr Tc1 Tc2 TRr Ttp2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE tCKED tCKED CKE DQMU, DQML Data bus DACK or EDACK Figure 26.27 Read Data: Two-State Expansion (CAS Latency 2) Rev.7.00 Mar.
Section 26 Electrical Characteristics 26.4.4 DMAC and EXDMAC Timing The DMAC and EXDMAC timings are shown below. T1 T2 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 26.28 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access Rev.7.00 Mar.
Section 26 Electrical Characteristics T1 T2 T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 26.29 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access Rev.7.00 Mar.
Section 26 Electrical Characteristics T1 T2 or T3 φ tTED tTED tETED tETED TEND0, TEND1 ETEND2, ETEND3 Figure 26.30 DMAC and EXDMAC TEND/ETEND Output Timing φ tDRQS tDRQH DREQ0, DREQ1 tEDRQS tDERQH EDREQ2, EDREQ3 Figure 26.31 DMAC and EXDMAC DREQ/EDREQ Input Timing φ tEDRKD tEDRKD EDRAK2, EDRAK3 Figure 26.32 EXDMAC EDRAK Output Timing Rev.7.00 Mar.
Section 26 Electrical Characteristics 26.4.5 Timing of On-Chip Peripheral Modules The on-chip peripheral module timings are shown below. T1 T2 φ tPRS tPRH Ports 1 to 8, A to H (read) tPWD Ports 1 to 3, 6 to 8, P53 to P50, ports A to H (write) Figure 26.33 I/O Port Input/Output Timing φ tPOD PO15 to PO0 Figure 26.34 PPG Output Timing φ tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 26.
Section 26 Electrical Characteristics φ tTCKS tTCKS TCLKA to TCLKD tTCKWH tTCKWL Figure 26.36 TPU Clock Input Timing φ tTMOD TMO0, TMO1 Figure 26.37 8-Bit Timer Output Timing φ tTMCS tTMCS TMCI0, TMCI1 tTMCWL tTMCWH Figure 26.38 8-Bit Timer Clock Input Timing φ tTMRS TMRI0, TMRI1 Figure 26.39 8-Bit Timer Reset Input Timing Rev.7.00 Mar.
Section 26 Electrical Characteristics φ tWOVD tWOVD WDTOVF Figure 26.40 WDT Output Timing tSCKW tSCKr tSCKf SCK0 to SCK2 tScyc Figure 26.41 SCK Clock Input Timing SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS tRXH RxD0 to RxD2 (receive data) Figure 26.42 SCI Input/Output Timing: Synchronous Mode φ tTRGS ADTRG Figure 26.43 A/D Converter External Trigger Input Timing Rev.7.00 Mar.
Section 26 Electrical Characteristics VIH SDA0 to SDA1 VIL tBUF tSTAH SCL0 to SCL1 P* tSTAS tSCLL tSCL tSP tSTOS Sr* S* tSf Note: tSCLH tSr P* tSDAS tSDAH S, P, and Sr represent the following conditions: S: Start condition P: Stop condition Sr: Retransmit start condition Figure 26.44 I2C Bus Interface 2 Input/Output Timing (Option) Rev.7.00 Mar.
Appendix Appendix A.
Appendix Port Name MCU Operating Mode Reset Hardware Standby Mode P97/DA5 1, 2, 4, 7 T T Software Standby Mode Bus Release State Program Execution State Sleep Mode [DAOE5 = 1] keep Input port keep Input port keep Input port keep Input port Input port keep [DAOE5 = 0] T P96/DA4 1, 2, 4, 7 T T [DAOE4 = 1] keep [DAOE4 = 0] T P95/DA3 1, 2, 4, 7 T T [DAOE3 = 1] keep [DAOE3 = 0] T P94/DA2 1, 2, 4, 7 T T [DAOE2 = 1] keep [DAOE2 = 0] T P93, P90 1, 2, 4, 7 T T T T PA7/A23 1
Appendix Port Name MCU Operating Mode Reset Hardware Standby Mode PA4/A20 3, 4, 7 T T PA3/A19 Software Standby Mode Bus Release State [OPE = 0, address output] [Address output] [Address output] T PA2/A18 [OPE = 1, address output] PA1/A17 PA0/A16 Program Execution State Sleep Mode T A20 to A16 [Other than the above] [Other than the above] keep I/O port T [Address output] keep [Other than the above] keep Port B 1, 2 L T [OPE = 0] T A15 to A8 [OPE = 1] keep 4 T T [OPE = 0, a
Appendix Port Name MCU Operating Mode Reset Hardware Standby Mode Port C 1, 2 T L Software Standby Mode Bus Release State Program Execution State Sleep Mode [OPE = 0] T [Address output] T A7 to A0 [OPE = 1] keep 4 T T [OPE = 0, address output] [Address output] [Address output] T A7 to A0 T [Other than the above] [Other than the above] keep I/O port [OPE = 1, address output] keep [Other than the above] keep *2 3, 5 , 7 T T [OPE = 0, address output] [Address output] [Address ou
Appendix Port Name MCU Operating Mode Reset Hardware Standby Mode Port E 1, 2, 4 3, 5*2, 7 PF7/φ PF6/AS Software Standby Mode Bus Release State Program Execution State Sleep Mode 8-bit bus T T keep keep I/O port 16-bit bus T T T T D7 to D0 8-bit bus T T keep keep I/O port 16-bit bus T T [Data bus] [Data bus] [Data bus] T T D7 to D0 [Other than the above] [Other than the above] [Other than the above] keep keep I/O port 1, 2, 4 Clock output T [Clock output] [Clo
Appendix Port Name MCU Operating Mode Reset Hardware Standby Mode PF5/RD 1, 2, 4 T H PF4/HWR Software Standby Mode Bus Release State Program Execution State Sleep Mode [OPE = 0] T RD, HWR [OPE = 0, RD, HWR output] [RD, HWR output] [RD, HWR output] T T RD, HWR [OPE = 1, RD, HWR output] [Other than the above] [Other than the above] H keep I/O port [OPE = 0, LWR output] [LWR output] [LWR output] T LWR T [Other than the above] [Other than the above] keep I/O port [OPE = 0, L
Appendix Port Name PF1/ UCAS/ DQMU*1 MCU Operating Mode Reset Hardware Standby Mode 1, 2, 4, 7 T T Software Standby Mode Bus Release State Program Execution State Sleep Mode [OPE = 0, UCAS (DQMU) output] [UCAS (DQMU) output] [UCAS (DQMU) output] T UCAS T [Other than the above] [Other than the above] keep I/O port [OPE = 1, UCAS (DQMU) output] H [Other than the above] keep PF0/WAIT PG6/BREQ 1, 2, 4, 7 1, 2, 4, 7 T T T T [WAIT input] [WAIT input] [WAIT input] T T WAIT [Other
Appendix Port Name PG4/ BREQO PG3/CS3 Program Execution State Sleep Mode MCU Operating Mode Reset Hardware Standby Mode Software Standby Mode 1, 2, 4, 7 T [BREQO output] [BREQO output] [BREQO output] 1, 2, 4, 7 T T T PG2/CS2 T BREQO BREQO [Other than the above] [Other than the above] [Other than the above] keep keep I/O port [OPE = 0, CS output] [CS output] [CS output] T CS [Other than the above] [Other than the above] keep I/O port [OPE = 0, CS output] [CS output] [CS out
Appendix Port Name PH3/OE/ CS7/CKE*1 MCU Operating Mode Reset Hardware Standby Mode 1, 2, 4, 7 T T Software Standby Mode Bus Release State Program Execution State Sleep Mode [OPE = 0, OE, CS, CKE output] [OE, CS, CKE output] [OE, CKE output] T OE, CKE T [Other than the above] [CS output] keep H [Other than the above] [OPE = 0, CS output] I/O port [OPE = 1, OE output] CS T [OPE = 1, CS output] H [OPE = 1, CKE output] L [Other than the above] keep PH2/CS6 1, 2, 4, 7 T T [OPE = 0,
Appendix Port Name PH1/CS5/ SDRAMφ*1 Bus Release State Program Execution State Sleep Mode [DCTL = 1] [DCTL = 1] Clock output Clock output [DCTL = 0, CS output] [DCTL = 0, CS output] T CS [Other than the above] [Other than the above] keep I/O port [OPE = 0, CS output] [CS output] [CS output] T CS T [Other than the above] [Other than the above] keep I/O port H H*3 MCU Operating Mode Reset Hardware Standby Mode 1, 2, 4, 7 [DCTL = 1] [DCTL = 1] [DCTL = 1] Clock output L [DCTL =
Appendix B.
Appendix C. Package Dimensions The package dimension that is shown in the Renesas Semiconductor Package Data Book has Priority. JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KC-A Previous Code FP-144H/FP-144HV MASS[Typ.] 1.4g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. HD *1 D 108 73 109 72 bp Reference Symbol c c1 HE Dimension in Millimeters Min Nom Max 20 D E 20 A2 1.
Appendix JEITA Package Code P-TFLGA145-9x9-0.65 RENESAS Code PTLG0145JB-A Previous Code - MASS[Typ.] 0.15g D w S B E w S A x4 v y1 S A S y S e A ZD e N M L K J B H G F E D ZE C B Reference Symbol Dimension in Millimeters Min 9.0 E 9.0 1 2 3 4 5 6 7 φb 8 9 10 11 12 13 0.15 w 0.20 A 1.2 A1 b 0.65 0.30 0.35 x φxn S A B Max v e A Nom D 0.40 0.08 y 0.1 y1 0.20 SD SE ZD 0.6 ZE 0.6 Figure C.2 Package Dimensions (TLP-145V) Rev.7.00 Mar.
Appendix D. Bus State during Execution of Instructions Table D.1 shows the execution state of each instruction in this LSI. [Explanation of Table Contents:] Order of execution Instruction 1 2 3 R:W 2nd 1 state of internal operation R:W EA 4 5 6 7 8 End of instruction Read the effective address in words. Read/write is not performed. Read the second word of the instruction that is being executed in words.
Appendix φ Address bus RD HWR, LWR High R: W 2nd Fetch of 3rd byte of instruction being executed Fetch of 4th byte of instruction being executed Internal operation R: W EA Fetch of 1st byte of Fetch of 2nd byte of brunch destination brunch destination instruction instruction Figure D.1 Timing of Address Bus, RD, HWR, and LWR (8-Bit Bus, 3-State Access, No Wait) Rev.7.00 Mar.
Appendix Table D.1 Instruction Execution State of Instructions 1 2 3 ADD.B #xx:8,Rd R:W NEXT ADD.B Rs,Rd R:W NEXT ADD.W #xx:16,Rd R:W 2nd R:W NEXT ADD.W Rs,Rd R:W NEXT ADD.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT ADD.L ERs,ERd R:W NEXT ADDS #1/2/4,ERd R:W NEXT ADDX #xx:8,Rd R:W NEXT ADDX Rs,Rd R:W NEXT AND.B #xx:8,Rd R:W NEXT AND.B Rs,Rd R:W NEXT AND.W #xx:16,Rd R:W 2nd R:W: NEXT AND.W Rs,Rd R:W NEXT AND.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT AND.
Appendix Instruction 1 2 3 4 BAND #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT BAND #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT BAND #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA BRA d:8 (BT d:8) R:W NEXT R:W EA BRN d:8 (BF d:8) R:W NEXT R:W EA BHI d:8 R:W NEXT R:W EA BLS d:8 R:W NEXT R:W EA BCC d:8 (BHS d:8) R:W NEXT R:W EA BCS d:8 (BLO d:8) R:W NEXT R:W EA BNE d:8 R:W NEXT R:W EA BEQ d:8 R:W NEXT R:W EA BVC d:8 R:W NEXT R:W EA BVS d:8 R:W NEXT R:W EA BPL d:8 R:W NEXT
Appendix Instruction 1 2 3 BRA d:16 (BT d:16) R:W 2nd 1 state of R:W EA internal operation BRN d:16 (BF d:16) R:W 2nd 1 state of R:W EA internal operation BHI d:16 R:W 2nd 1 state of R:W EA internal operation BLS d:16 R:W 2nd 1 state of R:W EA internal operation BCC d:16 (BHS d:16) R:W 2nd 1 state of R:W EA internal operation BCS d:16 (BLO d:16) R:W 2nd 1 state of R:W EA internal operation BNE d:16 R:W 2nd 1 state of R:W EA internal operation BEQ d:16 R:W 2nd 1 state of R:W EA internal op
Appendix Instruction 1 2 3 BGT d:16 R:W 2nd 1 state of R:W EA internal operation BLE d:16 R:W 2nd 1 state of R:W EA internal operation 4 5 6 7 8 9 BCLR #xx:3,Rd R:W NEXT BCLR #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT BCLR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th BCLR Rn,Rd R:W NEXT W:B EA R:B:M EA R:W:M NEXT BCLR Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR Rn,@aa:8 R:
Appendix Instruction 1 2 3 4 BILD #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT BILD #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT BILD #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA BIOR #xx:3,Rd R:W NEXT BIOR #xx:3,@ERd R:W 2nd R:B EA R:W NEXT BIOR #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT BIOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT BIOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA BIST #xx:3,Rd R:W NEXT BIST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BIST #xx:3,@aa:8 R:W 2nd R:B
Appendix Instruction 1 2 3 4 BLD #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT BLD #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT BLD #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA 5 6 7 8 9 R:W NEXT BNOT #xx:3,Rd R:W NEXT BNOT #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BNOT #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BNOT #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT BNOT #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th BNOT Rn,Rd R:W NEXT BNOT Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA
Appendix Instruction 1 2 3 4 BSET #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT BSET #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT BSET #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th BSET Rn,Rd R:W NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA BSET Rn,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BSET Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT BSET Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W EA 6 W:B EA BSET Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT BSR Advanced R:W d:8 NEXT 5 W:B EA W:B EA R:B:M EA R:W:M N
Appendix Instruction 1 2 BTST #xx:3,@aa:32 R:W 2nd R:W 3rd BTST Rn,Rd R:W NEXT 3 R:W 4th 4 R:B EA BTST Rn,@ERd R:W 2nd R:B EA R:W NEXT BTST Rn,@aa:8 R:W 2nd R:B EA R:W NEXT BTST Rn,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT BTST Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA 5 6 7 8 9 R:W NEXT R:W NEXT BXOR #xx:3,Rd R:W NEXT BXOR #xx:3,@ERd R:W 2nd R:B EA R:W NEXT BXOR #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT BXOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT BXOR #xx:3,@aa:32 R:W 2nd
Appendix Instruction 1 DAS Rd R:W NEXT DEC.B Rd R:W NEXT 2 3 4 5 6 DEC.W #1/2,Rd R:W NEXT DEC.L #1/2,ERd R:W NEXT DIVXS.B Rs,Rd R:W 2nd R:W NEXT 11 states of internal operation DIVXS.W Rs,ERd 19 states of internal operation R:W 2nd R:W NEXT DIVXU.B Rs,Rd R:W NEXT 11 states of internal operation DIVXU.W Rs,ERd R:W NEXT 19 states of internal operation EEPMOV.B R:W 2nd 2 states of internal operation R:B EAs W:B EAd R:W *1 *1 NEXT EEPMOV.
Appendix Instruction 1 2 3 4 5 JMP @@aa: 8 Advanced R:W NEXT R:W:M aa:8 R:W aa:8 1 State of R:W EA internal operation JSR @ERn Advanced R:W NEXT R:W EA W:W:M W:W Stack (H) Stack (L) JSR @aa:24 Advanced R:W 2nd 1 State of R:W EA internal operation JSR @@aa: 8 Advanced R:W NEXT R:W:M aa:8 6 7 8 9 W:W:M W:W Stack (H) Stack (L) R:W aa:8 W:W:M W:W R:W EA Stack (H) Stack (L) LDC #xx:8,CCR R:W NEXT LDC #xx:8,EXR R:W 2nd R:W NEXT LDC Rs,CCR R:W NEXT LDC Rs,EXR R:W NEXT LDC @ERs,CCR
Appendix Instruction 1 2 3 4 5 LDC @aa:16,CCR R:W 2nd R:W 3rd R:W NEXT R:W EA LDC @aa:16,EXR R:W 2nd R:W 3rd R:W NEXT R:W EA LDC @aa:32,CCR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA LDC @aa:32,EXR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA LDM.L @SP+, R:W 2nd R:W (ERn-ERn+1) *8 NEXT 1 State of R:W:M internal Stack operation (H)*2 R:W Stack (L) *2 LDM.L @SP+, R:W 2nd R:W (ERn-ERn+2) *8 NEXT 1 State of R:W:M internal Stack operation (H)*2 R:W Stack (L) *2 LDM.
Appendix Instruction 1 2 3 MOV.B @aa:8,Rd R:W NEXT MOV.B @aa:16,Rd R:W 2nd R:W NEXT R:B EA MOV.B @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT MOV.B Rs,@ERd R:W NEXT MOV.B Rs, @(d:16,ERd) R:W 2nd R:W NEXT W:B EA MOV.B Rs, @(d:32,ERd) R:W 2nd R:W 3rd R:W 4th MOV.B Rs,@-ERd R:W NEXT 1 State of W:B EA internal operation MOV.B Rs,@aa:8 R:W NEXT W:B EA MOV.B Rs,@aa:16 R:W 2nd R:W NEXT W:B EA MOV.B Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT MOV.W #xx:16,Rd R:W 2nd R:W NEXT MOV.
Appendix Instruction 1 2 3 MOV.W Rs,@ERd R:W NEXT MOV.W Rs, @(d:16,ERd) R:W 2nd R:W NEXT W:W EA MOV.W Rs, @(d:32,ERd) R:W 2nd R:W 3rd R:W 4th MOV.W Rs,@-ERd R:W NEXT MOV.W Rs,@aa:16 R:W 2nd R:W NEXT W:W EA MOV.W Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT MOV.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT 4 5 6 7 W:W EA R:W NEXT W:W EA 1 State of W:W EA internal operation W:W EA MOV.L ERs,ERd R:W NEXT MOV.L @ERs,ERd R:W 2nd R:W NEXT R:W:M EA R:W EA+2 MOV.
Appendix Instruction 1 2 3 4 5 MOV.L ERs,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W:M EA W:W EA+2 MOV.L ERs,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W:M EA MOVFPE @aa:16,Rd Not available in this LSI. 6 7 8 9 W:W EA+2 MOVTPE Rs,@aa:16 MULXS.B Rs,Rd R:W 2nd R:W NEXT 2 State of internal operation MULXS.W Rs,ERd 3 State of internal operation R:W 2nd R:W NEXT MULXU.B Rs,Rd R:W NEXT 2 State of internal operation MULXU.W Rs,ERd R:W NEXT 3 State of internal operation NEG.
Appendix Instruction OR.L ERs,ERd 1 2 3 4 5 R:W 2nd R:W NEXT ORC #xx:8,CCR R:W NEXT ORC #xx:8,EXR R:W 2nd R:W NEXT POP.W Rn R:W NEXT 1 State of R:W EA internal operation POP.L ERn R:W 2nd R:W NEXT PUSH.W Rn R:W NEXT PUSH.L ERn R:W 2nd R:W NEXT ROTL.B Rd R:W NEXT ROTL.B #2,Rd R:W NEXT ROTL.W Rd R:W NEXT 1 State of R:W:M internal EA operation 1 State of W:W EA internal operation 1 State of W:W:M internal EA operation ROTL.W #2,Rd R:W NEXT ROTL.L ERd R:W NEXT ROTL.
Appendix Instruction ROTXL.B Rd 1 2 3 4 5 6 7 8 9 R:W NEXT ROTXL.B #2,Rd R:W NEXT ROTXL.W Rd R:W NEXT ROTXL.W #2,Rd R:W NEXT ROTXL.L ERd R:W NEXT ROTXL.L #2,ERd R:W NEXT ROTXR.B Rd R:W NEXT ROTXR.B #2,Rd R:W NEXT ROTXR.W Rd R:W NEXT ROTXR.W #2,Rd R:W NEXT ROTXR.L ERd R:W NEXT ROTXR.L #2,ERd R:W NEXT RTE R:W NEXT RTS Advanced R:W NEXT SHAL.B Rd R:W NEXT SHAL.B #2,Rd R:W NEXT SHAL.
Appendix Instruction 1 2 3 SHAL.L #2,ERd R:W NEXT SHAR.B Rd R:W NEXT SHAR.B #2,Rd R:W NEXT SHAR.W Rd R:W NEXT SHAR.W #2,Rd R:W NEXT SHAR.L ERd R:W NEXT SHAR.L #2,ERd R:W NEXT SHLL.B Rd R:W NEXT SHLL.B #2,Rd R:W NEXT SHLL.W Rd R:W NEXT SHLL.W #2,Rd R:W NEXT SHLL.L ERd R:W NEXT SHLL.L #2,ERd R:W NEXT SHLR.B Rd R:W NEXT SHLR.B #2,Rd R:W NEXT SHLR.W Rd R:W NEXT SHLR.W #2,Rd R:W NEXT SHLR.L ERd R:W NEXT SHLR.L #2,ERd R:W NEXT Rev.7.00 Mar.
Appendix Instruction 1 2 3 4 5 6 SLEEP R:W NEXT STC CCR,Rd R:W NEXT STC EXR,Rd R:W NEXT STC CCR,@ERd R:W 2nd R:W NEXT W:W EA STC EXR,@ERd R:W 2nd R:W NEXT W:W EA STC CCR, @(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA STC EXR, @(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA STC CCR, @(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA STC EXR, @(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA STC CCR, @-ERd R:W 2nd R:W NEXT 1 state of W:W EA internal operat
Appendix Instruction 1 2 STM.L (ERnERn+3), @-SP*8 R:W 2nd R:W NEXT STMAC MACH,ERd R:W NEXT STMAC MACL,ERd R:W NEXT SUB.B Rs,Rd R:W NEXT SUB.W #xx:16,Rd R:W 2nd R:W NEXT SUB.W Rs,Rd R:W NEXT SUB.L #xx:32,ERd R:W 2nd R:W 3rd 3 4 5 6 7 8 9 1 state of W:W:M W:W internal Stack (H) Stack (L) *2 operation *2 R:W NEXT SUB.
Appendix Instruction 1 2 3 4 5 XORC #xx:8,CCR R:W NEXT XORC #xx:8,EXR R:W 2nd R:W NEXT Reset R:W:M VEC R:W VEC+2 R:W *5 1 state of W:W W:W W:W internal Stack (L) Stack (H) Stack operation (EXR) Advanced exception handling Interrupt exception handling Advanced 6 7 8 9 1 state of R:W *4 internal operation R:W:M VEC R:W VEC+2 1 state of R:W *6 internal operation Notes: 1. EAs is the ER5 value and EAd the ER6 value. 1 is added to each of them after execution.
Appendix Rev.7.00 Mar.
Index Index 16-Bit Timer Pulse Unit (TPU) .............. 545 Buffer Operation ................................. 591 Cascaded Operation ............................ 596 Input Capture Function ....................... 588 Phase Counting Mode......................... 603 PWM Modes....................................... 598 Synchronous Operation....................... 589 Toggle output...................................... 587 Waveform Output by Compare Match ..................................................
Index Single Address Mode.......................... 320 Transfer Mode .................................... 309 Write Data Buffer Function ................ 346 DRAM Interface ..................................... 191 Effective Address...................................... 62 effective address extension ....................... 61 Effective Address Extension..................... 61 Exception Handling .................................. 93 Interrupt Exception Handling ...............
Index Interrupt Exception Handling Vector Table ....................................................... 121 Interrupt Mask Bit..................................... 46 Interrupt Priority Register (IPR) ............. 103 Interrupt Request Mask Level................... 45 Interrupts ADI ..................................................... 816 CMI..................................................... 122 CMIA.................................................. 669 CMIA0...........................................
Index Register States in Each Operating Mode................................................. 1007 MCU Operating Modes ............................ 71 Open-drain control register ..................... 455 Operation Field ......................................... 61 PLL Circuit ............................................. 961 Port Function Control Register 1 ............ 509 Port Function Control Register 2 ............ 485 Port register............................................. 455 Program Counter.....
Index IrCR .......................... 720, 983, 996, 1008 ISCR ......................... 110, 983, 995, 1008 ISR .......................... 116, 987, 1001, 1012 ITSR.......................... 117, 983, 995, 1008 MAR ......................... 283, 986, 999, 1011 MDCR ...................... 72, 987, 1001, 1012 MRA ......................... 427, 982, 993, 1007 MRB ......................... 429, 982, 993, 1007 MSTPCR ................ 970, 987, 1001, 1012 NDER ............. 634, 987, 988, 1001, 1012 NDR........
Index SSIER ....................... 119, 983, 995, 1008 SSR ........................... 703, 984, 997, 1009 SYSCR...................... 72, 987, 1001, 1012 TCNT........................ 656, 985, 997, 1009 TCORA................... 656, 990, 1004, 1015 TCORB ................... 656, 990, 1004, 1015 TCR ................... 552, 657, 984, 990, 997, ..................................... 1009, 1015, 1016 TCSR ...................... 679, 990, 1004, 1015 TDR .......................... 694, 984, 996, 1009 TGR .....
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2378, H8S/2378R Group Publication Date: 1st Edition, September 2001 Rev.7.00, March 18, 2009 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. ©2009. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
H8S/2378, H8S/2378R Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0109-0700
