Datasheet

Section 24 Power-Down Modes
Rev.7.00 Mar. 18, 2009 page 967 of 1136
REJ09B0109-0700
Notes: Halted (Retained) in the table means that internal register values are retained and
internal operations are suspended.
Halted (Reset) in the table means that internal register values and internal states are
initialized.
In module stop mode, only modules for which a stop setting has been made are halted
(reset or retained).
1. The active or halted state can be selected by means of the MSTP0 bit in MSTPCR.
2. Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
3. TDR, SSR, and RDR are halted (reset) and other registers are halted (retained).
4. BC2 to BC0 are halted (reset) and other registers are halted (retained).
Program-halted stateProgram execution state
High-speel mode
(Internal clock is PLL
circuit output clock)
Reset state
STBY pin = low
STBY pin = high
RES pin = low
SSBY = 0
MSTPCR =
H'FFFF (H'FFFE),
EXMSTPCR = H'FFFF,
SSBY = 0
SSBY = 1
SCK2 to
SCK0 ≠ 0
RES pin = high
SCK2 to
SCK0 = 0
SLEEP
instruction
Interrupt
*1
: Transition after exception handling : Power- down mode
SLEEP
instruction
Any interrupt
SLEEP
instruction
External
interrupt
*2
Notes: • From any state, a transition to hardware standby mode occurs when STBY is driven low.
• From any state except hardware standby mode, a transition to the reset state occurs
when RES is driven low.
1. NMI, IRQ0 to IRQ15, 8-bit timer interrupts, watchdog timer interrupts.
(8-bit timer interrupts are valid when MSTP0 = 0.)
2. NMI, IRQ0 to IRQ15
(IRQ0 to IRQ15 are valid when the corresponding bit in SSIER is 1.)
Hardware
standby mode
Sleep mode
All
module-clocks-stop
mode
Software
standby mode
Clock division
mode
Figure 24.1 Mode Transitions