Datasheet

Section 24 Power-Down Modes

Rev.7.00 Mar. 18, 2009 page 979 of 1136

REJ09B0109-0700

All-module-clocks-stop mode is cleared by an external interrupt (NMI, IRQ0 to IRQ7 pins), RES

pin input, or an internal interrupt (8-bit timer, watchdog timer), and the CPU returns to the normal

program execution state via the exception handling state. All-module-clocks-stop mode is not

cleared if interrupts are disabled, if interrupts other than NMI are masked by the CPU, or if the

relevant interrupt is designated as a DTC activation source.

When the STBY pin is driven low, a transition is made to hardware standby mode.

24.3 φ Clock Output Control

Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the

corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle,

and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR

for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set.

Table 24.3 shows the state of the φ pin in each processing state.

Table 24.3 φ Pin State in Each Processing State

DDR PSTOP

Normal operating

state

Sleep mode

Software

standby mode

Hardware

standby mode

All-module-

clocks-stop

mode

0 X High impedance High impedance High impedance High impedance High impedance

1 0 φ output φ output Fixed high High impedance φ output

1 1 Fixed high Fixed high Fixed high High impedance Fixed high

24.4 Usage Notes

24.4.1 I/O Port Status

In software standby mode, I/O port states are retained. Therefore, there is no reduction in current

dissipation for the output current when a high-level signal is output.

24.4.2 Current Dissipation during Oscillation Stabilization Standby Period

Current dissipation increases during the oscillation stabilization standby period.