Datasheet

Section 26 Electrical Characteristics
Rev.7.00 Mar. 18, 2009 page 1024 of 1136
REJ09B0109-0700
(1) Clock Timing
Table 26.5 Clock Timing
Conditions: V
CC
= 3.0 V to 3.6 V, AV
CC
= 3.0 V to 3.6 V, V
ref
= 3.0 V to AV
CC
, V
SS
= AV
SS
=
0 V, φ = 8 MHz to 33 MHz, T
a
= −20°C to +75°C (regular specifications),
T
a
= −40°C to +85°C (wide-range specifications)
Item Symbol Min. Max. Unit Test Conditions
Clock cycle time t
cyc
30.3 125 ns Figure 26.2
Clock pulse high width t
CH
10 ⎯ ns Figure 26.2
Clock pulse low width t
CL
10 ⎯ ns
Clock rising time t
Cr
⎯ 5 ns
Clock falling time t
Cf
⎯ 5 ns
Reset oscillation settling time
(crystal)
t
OSC1
10 ⎯ ms Figure 26.4(1)
Software standby oscillation
settling time (crystal)
t
OSC2
10 ⎯ ms Figure 26.4(2)
External clock output delay
settling time
t
DEXT
1 ⎯ ms Figure 26.4(1)
Clock phase difference
*
t
cdif
1/4 × t
cyc
−3 1/4 × t
cyc
+3 ns Figure 26.3
Clock pulse high width
(SDRAMφ)
*
t
SDCH
10 ⎯ ns Figure 26.3
Clock pulse low width
(SDRAMφ)
*
t
SDCL
10 ⎯ ns Figure 26.3
Clock rising time (SDRAMφ)
*
t
sdcr
⎯ 5 ns Figure 26.3
Clock falling time (SDRAMφ)
*
t
sdcf
⎯ 5 ns Figure 26.3
Note: * Not supported by the H8S/2378 Group.