Datasheet

Section 26 Electrical Characteristics
Rev.7.00 Mar. 18, 2009 page 1079 of 1136
REJ09B0109-0700
Tp
φ
A23 to A0
RAS5 to RAS2
UCAS
LCAS
OE, RD
HWR
D15 to D0
OE, RD
HWR
D15 to D0
AS
Tr Tc1
t
CPW1
t
AC3
t
RCH
t
RCS1
Tc2 Tc1 Tc2
Read
Write
DACK and EDACK timing: when DDS = 0 and EDDS = 0
RAS timing: when RAST = 0
Note:
DACK0, DACK1
EDACK2, EDACK3
t
DACD1
t
DACD2
t
EDACD1
t
EDACD2
Figure 26.16 DRAM Access Timing: Two-State Burst Access