Datasheet

Section 26 Electrical Characteristics
Rev.7.00 Mar. 18, 2009 page 1088 of 1136
REJ09B0109-0700
26.4.4 DMAC and EXDMAC Timing
The DMAC and EXDMAC timings are shown below.
T
1
φ
A
23 to A0
CS7 to CS0
AS
t
DACD1
t
DACD2
t
EDACD1
t
EDACD2
RD
(read)
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
DACK0, DACK1
EDACK2, EDACK3
T
2
Figure 26.28 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access