Datasheet

Section 26 Electrical Characteristics
Rev.7.00 Mar. 18, 2009 page 1091 of 1136
REJ09B0109-0700
26.4.5 Timing of On-Chip Peripheral Modules
The on-chip peripheral module timings are shown below.
T
1
t
PRS
t
PRH
t
PWD
T
2
φ
Ports 1 to 8, A to H
(read)
Ports 1 to 3, 6 to 8,
P53 to P50,
ports A to H
(write)
Figure 26.33 I/O Port Input/Output Timing
φ
PO15 to PO0
t
POD
Figure 26.34 PPG Output Timing
φ
Output compare
output*
Input capture
input*
t
TOCD
t
TICS
Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3
Figure 26.35 TPU Input/Output Timing