Datasheet

Section 5 Interrupt Controller
Rev.7.00 Mar. 18, 2009 page 105 of 1136
REJ09B0109-0700
5.2 Input/Output Pins
Table 5.1 shows the pin configuration of the interrupt controller.
Table 5.1 Pin Configuration
Name I/O Function
NMI Input Nonmaskable external interrupt
Rising or falling edge can be selected.
IRQ15 to IRQ0 Input Maskable external interrupts
Rising, falling, or both edges, or level sensing, can be selected.
5.3 Register Descriptions
The interrupt controller has the following registers.
• Interrupt control register (INTCR)
• IRQ sense control register H (ISCRH)
• IRQ sense control register L (ISCRL)
• IRQ enable register (IER)
• IRQ status register (ISR)
• IRQ pin select register (ITSR)
• Software standby release IRQ enable register (SSIER)
• Interrupt priority register A (IPRA)
• Interrupt priority register B (IPRB)
• Interrupt priority register C (IPRC)
• Interrupt priority register D (IPRD)
• Interrupt priority register E (IPRE)
• Interrupt priority register F (IPRF)
• Interrupt priority register G (IPRG)
• Interrupt priority register H (IPRH)
• Interrupt priority register I (IPRI)
• Interrupt priority register J (IPRJ)
• Interrupt priority register K (IPRK)