Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 137 of 1136
REJ09B0109-0700
Section 6 Bus Controller (BSC)
This LSI has an on-chip bus controller (BSC) that manages the external address space divided into
eight areas.
The bus controller also has a bus arbitration function, and controls the operation of the bus
mastership⎯the CPU, DMA controller (DMAC), EXDMA controller (EXDMAC)
*
, and data
transfer controller (DTC). A block diagram of the bus controller is shown in figure 6.1.
Note: * The EXDMAC is not supported by the H8S/2375, H8S/2375R, H8S/2373, and
H8S/2373R.
6.1 Features
• Manages external address space in area units
Manages the external address space divided into eight areas of 2 Mbytes
Bus specifications can be set independently for each area
Burst ROM, DRAM, or synchronous DRAM interface
*
can be set
• Basic bus interface
Chip select signals (CS0 to CS7) can be output for areas 0 to 7
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
• Burst ROM interface
Burst ROM interface can be set independently for areas 0 and 1
• DRAM interface
DRAM interface can be set for areas 2 to 5
• Synchronous DRAM interface
*
Continuous synchronous DRAM space can be set for areas 2 to 5
• Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership between the CPU, DMAC, DTC, and
EXDMAC
Note: * The Synchronous DRAM interface is not supported by the H8S/2378 Group.
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