Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 152 of 1136
REJ09B0109-0700
T
h
Address
φ
T
1
T
2
T
3
T
t
Bus cycle
Data
HWR, LWR
Write
Data
RD
CS
Read
Figure 6.3 CS and Address Assertion Period Extension
(Example of 3-State Access Space and RDNn = 0)
