Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 157 of 1136
REJ09B0109-0700
Bit Bit Name Initial Value R/W Description
12 CAST 0 R/W Column Address Output Cycle Number Select
Selects whether the column address output cycle in
DRAM access comprises 3 states or 2 states. The
setting of this bit applies to all areas designated as
DRAM space.
0: Column address output cycle comprises
2 states
1: Column address output cycle comprises
3 states
11 — 0 R/W Reserved
This bit can be read from or written to. However,
the write value should always be 0.