Datasheet

Rev.7.00 Mar. 18, 2009 page xxi of lxvi
REJ09B0109-0700
Item Page Revision (See Manual for Details)
26.4.3 Bus Timing
Figure 26.11 Basic
Bus Timing: Three-
State Access (CS
Assertion Period
Extended)
1074 Figure amended
EDACK2, EDACK3
t
EDACD1
t
EDACD2
Figure 26.14 DRAM
Access Timing: Two-
State Access
1077 Figure amended
EDACK2, EDACK3
t
EDACD1
t
EDACD2
Figure 26.15 DRAM
Access Timing: Two-
State Access, One
Wait
1078 Figure amended
EDACK2, EDACK3
Figure 26.16 DRAM
Access Timing: Two-
State Burst Access
1079 Figure amended
EDACK2, EDACK3
t
EDACD1
t
EDACD2
Figure 26.17 DRAM
Access Timing: Three-
State Access (RAST =
1)
1080 Figure amended
EDACK2, EDACK3
t
EDACD1
t
EDACD2
Figure 26.18 DRAM
Access Timing: Three-
State Burst Access
1081 Figure amended
EDACK2, EDACK3
26.4.4 DMAC and
EXDMAC Timing
Figure 26.28 DMAC
and EXDMAC Single
Address Transfer
Timing: Two-State
Access
1088 Figure amended
t
EDACD1
t
EDACD2
EDACK2, EDACK3
Figure 26.29 DMAC
and EXDMAC Single
Address Transfer
Timing: Three-State
Access
1089 Figure amended
t
EDACD1
t
EDACD2
EDACK2, EDACK3