Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 165 of 1136
REJ09B0109-0700
Bit Bit Name Initial Value R/W Description
10 ⎯ 0 R/W Reserved
This bit can be read from or written to. However,
the write value should always be 0.
9
8
RCD1
RCD0
0
0
R/W
R/W
RAS-CAS Wait Control
These bits select a wait cycle to be inserted
between the RAS assert cycle and CAS assert
cycle. A 1- to 4-state wait cycle can be inserted.
00: Wait cycle not inserted
01: 1-state wait cycle inserted
10: 2-state wait cycle inserted
11: 3-state wait cycle inserted
7 to 4 ⎯ All 0 R/W Reserved
These bits can be read from or written to. However,
the write value should always be 0.
3 CKSPE
*
0 R/W Clock Suspend Enable
Enables clock suspend mode for extend read data
during DMAC and EXDMAC single address
transfer with the synchronous DRAM interface.
0: Disables clock suspend mode
1: Enables clock suspend mode
2 ⎯ 0 R/W Reserved
This bit can be read from or written to. However,
the write value should always be 0.
1
0
RDXC1
*
RDXC0
*
0
0
R/W
R/W
Read Data Extension Cycle Number Selection
Selects the number of read data extension cycle
(Tsp) insertion state in clock suspend mode. These
bits are valid when the CKSPE bit is set to 1.
00: Inserts 1 state
01: Inserts 2 state
10: Inserts 3 state
11: Inserts 4 state
Note: * Not used in the H8S/2378 Group. Do not change the initial value.