Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 180 of 1136
REJ09B0109-0700
8-Bit, 3-State Access Space: Figure 6.11 shows the bus timing for an 8-bit, 3-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The
LWR pin is always fixed high. Wait states can be inserted.
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
LWR
D15 to D8
Valid
D7 to D0
Write
High
T
3
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.11 Bus Timing for 8-Bit, 3-State Access Space
16-Bit, 2-State Access Space: Figures 6.12 to 6.14 show bus timings for a 16-bit, 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used