Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 186 of 1136
REJ09B0109-0700
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D15 to D8
Valid
D7 to D0
Valid
Read
HWR
LWR
D15 to D8
Valid
D7 to D0
Valid
Write
T
3
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space
(Word Access)
