Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 200 of 1136
REJ09B0109-0700
By program wait
T
p
Address bus
φ
WAIT
T
r
T
c1
T
w
T
w
T
c2
By WAIT pin
RASn (CSn)
Read
Write
UCAS, LCAS
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
Row address Column address
High
High
Note: Downward arrows indicate the timing of WAIT pin sampling.
n = 2 to 5
Figure 6.26 Example of Wait State Insertion Timing
(2-State Column Address Output)