Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 225 of 1136
REJ09B0109-0700
6.7.9 Precharge State Count
When the interval specification from the PALL command to the next ACTV/REF command
cannot be satisfied, from one to four T
p
states can be selected by setting bits TPC1 and TPC0 in
DRACCR. Set the optimum number of T
p
cycles according to the synchronous DRAM connected
and the operating frequency of this LSI. Figure 6.47 shows the timing when two Tp states are
inserted.