Datasheet

Rev.7.00 Mar. 18, 2009 page xxviii of lxvi
REJ09B0109-0700
7.5.3 Idle Mode.............................................................................................................. 314
7.5.4 Repeat Mode......................................................................................................... 316
7.5.5 Single Address Mode............................................................................................ 320
7.5.6 Normal Mode........................................................................................................ 323
7.5.7 Block Transfer Mode............................................................................................ 326
7.5.8 Basic Bus Cycles................................................................................................... 331
7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles................................................ 332
7.5.10 DMA Transfer (Single Address Mode) Bus Cycles.............................................. 340
7.5.11 Write Data Buffer Function .................................................................................. 346
7.5.12 Multi-Channel Operation...................................................................................... 347
7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles,
and EXDMAC ...................................................................................................... 349
7.5.14 DMAC and NMI Interrupts................................................................................... 350
7.5.15 Forced Termination of DMAC Operation............................................................. 351
7.5.16 Clearing Full Address Mode................................................................................. 352
7.6 Interrupt Sources................................................................................................................ 353
7.7 Usage Notes ....................................................................................................................... 354
7.7.1 DMAC Register Access during Operation............................................................ 354
7.7.2 Module Stop.......................................................................................................... 355
7.7.3 Write Data Buffer Function .................................................................................. 356
7.7.4 TEND Output........................................................................................................ 356
7.7.5 Activation by Falling Edge on DREQ Pin ............................................................ 357
7.7.6 Activation Source Acceptance.............................................................................. 358
7.7.7 Internal Interrupt after End of Transfer................................................................. 358
7.7.8 Channel Re-Setting ............................................................................................... 358
Section 8 EXDMA Controller (EXDMAC) ...................................................... 359
8.1 Features.............................................................................................................................. 359
8.2 Input/Output Pins............................................................................................................... 361
8.3 Register Descriptions......................................................................................................... 362
8.3.1 EXDMA Source Address Register (EDSAR)....................................................... 362
8.3.2 EXDMA Destination Address Register (EDDAR)............................................... 362
8.3.3 EXDMA Transfer Count Register (EDTCR)........................................................ 363
8.3.4 EXDMA Mode Control Register (EDMDR) ........................................................ 365
8.3.5 EXDMA Address Control Register (EDACR) ..................................................... 370
8.4 Operation............................................................................................................................ 374
8.4.1 Transfer Modes..................................................................................................... 374
8.4.2 Address Modes ..................................................................................................... 375
8.4.3 DMA Transfer Requests ....................................................................................... 379
8.4.4 Bus Modes ............................................................................................................ 379
8.4.5 Transfer Modes..................................................................................................... 381