Datasheet

Rev.7.00 Mar. 18, 2009 page xxix of lxvi
REJ09B0109-0700
8.4.6 Repeat Area Function ........................................................................................... 383
8.4.7 Registers during DMA Transfer Operation........................................................... 385
8.4.8 Channel Priority Order.......................................................................................... 390
8.4.9 EXDMAC Bus Cycles (Dual Address Mode)....................................................... 393
8.4.10 EXDMAC Bus Cycles (Single Address Mode).................................................... 400
8.4.11 Examples of Operation Timing in Each Mode...................................................... 405
8.4.12 Ending DMA Transfer .......................................................................................... 418
8.4.13 Relationship between EXDMAC and Other Bus Masters .................................... 419
8.5 Interrupt Sources................................................................................................................ 420
8.6 Usage Notes ....................................................................................................................... 422
8.6.1 EXDMAC Register Access during Operation ...................................................... 422
8.6.2 Module Stop State................................................................................................. 422
8.6.3 EDREQ Pin Falling Edge Activation.................................................................... 422
8.6.4 Activation Source Acceptance.............................................................................. 423
8.6.5 Enabling Interrupt Requests when IRF = 1 in EDMDR ....................................... 423
8.6.6 ETEND Pin and CBR Refresh Cycle.................................................................... 423
Section 9 Data Transfer Controller (DTC) ........................................................425
9.1 Features.............................................................................................................................. 425
9.2 Register Descriptions......................................................................................................... 427
9.2.1 DTC Mode Register A (MRA) ............................................................................. 427
9.2.2 DTC Mode Register B (MRB).............................................................................. 429
9.2.3 DTC Source Address Register (SAR)................................................................... 429
9.2.4 DTC Destination Address Register (DAR)........................................................... 429
9.2.5 DTC Transfer Count Register A (CRA) ............................................................... 430
9.2.6 DTC Transfer Count Register B (CRB)................................................................ 430
9.2.7 DTC Enable Registers A to H (DTCERA to DTCERH) ...................................... 430
9.2.8 DTC Vector Register (DTVECR)......................................................................... 431
9.3 Activation Sources ............................................................................................................. 432
9.4 Location of Register Information and DTC Vector Table ................................................. 433
9.5 Operation............................................................................................................................ 437
9.5.1 Normal Mode........................................................................................................ 440
9.5.2 Repeat Mode......................................................................................................... 441
9.5.3 Block Transfer Mode............................................................................................ 442
9.5.4 Chain Transfer ...................................................................................................... 443
9.5.5 Interrupt Sources................................................................................................... 444
9.5.6 Operation Timing.................................................................................................. 444
9.5.7 Number of DTC Execution States ........................................................................ 445
9.6 Procedures for Using DTC................................................................................................. 447
9.6.1 Activation by Interrupt.......................................................................................... 447
9.6.2 Activation by Software ......................................................................................... 447