Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 243 of 1136
REJ09B0109-0700
When DDS = 0 or EDDS = 0: When continuous synchronous DRAM space is accessed in
DMAC or EXDMAC single address transfer mode, full access (normal access) is always
performed. With the synchronous DRAM interface, the DACK or EDACK output goes low from
the T
r
state.
In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used
when accessing continuous synchronous DRAM space.
Figure 6.61 shows the DACK or EDACK output timing for connecting the synchronous DRAM
interface when DDS = 0 or EDDS = 0.