Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 262 of 1136
REJ09B0109-0700
not inserted after continuous synchronous DRAM space read access even if bits ICIS1 and
ICIS0 are set to 1.
T
p
Address bus
Idle cycle
Data bus
T
r
T
c1
T
cl
T
c2
T
3
T
i
T
c1
Continuous synchronous
DRAM space read External space read
Continuous synchronous
DRAM space read
T
2
T
i
T
1
RAS
CAS
WE
RD
CKE
High
PALL ACTV READ NOP
NOPREAD
DQMU, DQML
T
Cl
T
c2
Precharge-sel
φ
External address
External address
Column address 1 Column address 2
Row
address
Row
address
Column
address
Figure 6.79 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2)