Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 265 of 1136
REJ09B0109-0700
Previous Access Next Access ICIS2 ICIS1 ICIS0 DRMI IDLC Idle cycle
0 ⎯ ⎯ ⎯ ⎯ Disabled
1 ⎯ ⎯ ⎯ 0 1 state inserted
Normal space read
1 2 states inserted
0 ⎯ ⎯ ⎯ ⎯ Disabled
1 ⎯ ⎯ ⎯ 0 1 state inserted
Normal space write
DRAM
*
/continuous
synchronous DRAM
space read
1 2 states inserted
0 ⎯ ⎯ ⎯ ⎯ Disabled
1 ⎯ ⎯ ⎯ 0 1 state inserted
Normal space read
1 2 states inserted
0 ⎯ ⎯ ⎯ ⎯ Disabled
DRAM/continuous
synchronous DRAM
*
space write
1 ⎯ ⎯ ⎯ 0 1 state inserted
DRAM
*
/continuous
synchronous DRAM
space read
1 2 states inserted
Note: * Not supported by the H8S/2378 Group.
Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of
consecutive read and write operations in DRAM/continuous synchronous DRAM space burst
access. Figures 6.81 and 6.82 show an example of the timing for idle cycle insertion in the case of
consecutive read and write accesses to DRAM/continuous synchronous DRAM space.