Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Mar. 18, 2009 page 279 of 1136
REJ09B0109-0700
Section 7 DMA Controller (DMAC)
This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4
channels.
7.1 Features
• Selectable as short address mode or full address mode
Short address mode
⎯ Maximum of 4 channels can be used
⎯ Dual address mode or single address mode can be selected
⎯ In dual address mode, one of the two addresses, transfer source and transfer destination, is
specified as 24 bits and the other as 16 bits
⎯ In single address mode, transfer source or transfer destination address only is specified as
24 bits
⎯ In single address mode, transfer can be performed in one bus cycle
⎯ Choice of sequential mode, idle mode, or repeat mode for dual address mode and single
address mode
Full address mode
⎯ Maximum of 2 channels can be used
⎯ Transfer source and transfer destination addresses as specified as 24 bits
⎯ Choice of normal mode or block transfer mode
• 16-Mbyte address space can be specified directly
• Byte or word can be set as the transfer unit
• Activation sources: internal interrupt, external request, auto-request (depending on transfer
mode)
⎯ Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts
⎯ Serial communication interface (SCI_0, SCI_1) transmission complete interrupt, reception
complete interrupt
⎯ A/D converter conversion end interrupt
⎯ External request
⎯ Auto-request
• Module stop mode can be set
DMAS260A_010020020400