Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Mar. 18, 2009 page 297 of 1136
REJ09B0109-0700
Bit Bit Name Initial Value R/W Description
13, 12 — All 0 R/W Reserved
These bits can be read from or written to. However,
the write value should always be 0.
11 DTA1 0 R/W
Data Transfer Acknowledge 1
These bits enable or disable clearing when DMA
transfer is performed for the internal interrupt
source selected by the DTF3 to DTF0 bits in
DMACR of channel 1.
It the DTA1 bit is set to 1 when DTE1 = 1, the
internal interrupt source is cleared automatically by
DMA transfer. When DTE1 = 1 and DTA1 = 1, the
internal interrupt source does not issue an interrupt
request to the CPU or DTC.
It the DTA1 bit is cleared to 0 when DTE1 = 1, the
internal interrupt source is not cleared when a
transfer is performed, and can issue an interrupt
request to the CPU or DTC in parallel. In this case,
the interrupt source should be cleared by the CPU
or DTC transfer.
When DTE1 = 0, the internal interrupt source
issues an interrupt request to the CPU or DTC
regardless of the DTA1 bit setting.
The state of the DTME1 bit does not affect the
above operations.
10 — 0 R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.